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參數(shù)資料
| 型號(hào)： | ICS9248YF-172-T |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁(yè)數(shù)： | 1/16頁(yè) |
| 文件大小： | 319K |
| 代理商： | ICS9248YF-172-T |
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Integrated
Circuit
Systems, Inc.
ICS9248-172
Third party brands and names are the property of their respective owners.
Block Diagram
9248-172 Rev - 02/12/01
Functionality
Pin Configuration
48-Pin 300mil SSOP & 240mil TSSOP
Recommended Application:
ALI 1651 style chipset
Output Features:
2 - CPU clocks @ 2.5V
13 - SDRAM @ 3.3V
7 - PCI @3.3V
2 - AGP @ 3.3V
1 - IOAPIC @ 2.5V
1 - 48MHz, @3.3V
1 - REF @3.3V, (selectable strength) through I
2C
Features:
Up to 147MHz frequency support
Support power management: CPU stop, PCI stop and
Power down.
Spread spectrum for EMI control (0 to -0.5% down
spread, ± 0.25% center spread).
Uses external 14.318MHz crystal
Skew Specifications:
CPU - CPU: <250ps
PCI - PCI: <500ps
SDRAM - SDRAM: <250ps
AGP - AGP: <250ps
PCI - AGP: <750ps
CPU - SDRAM:<350ps
CPU - PCI: <3ns
PII/III System Clock Chip
Notes:
REF0 can be 1X or 2X strength controlled by I2C.
* Internal Pull-up Resistor of 120K to VDD.
** Internal Pull-down of 120K to GND.
1. This input has 2X drive strength.
PLL2
PLL1
Spread
Spectrum
48MHz
CPUCLK (1:0)
IOAPIC
SDRAM (12:0)
PCICLK (5:0)
AGP (1:0)
2
6
13
2
PCICLK_F
X1
X2
XTAL
OSC
CPU
DIVDER
SDRAM
DIVDER
PCI
DIVDER
AGP
DIVDER
Stop
SDATA
SCLK
FS (3:0)
PD#
PCI_STOP#
CPU_STOP#
MODE
Control
Logic
Config.
Reg.
REF0
Note:
PCICLK = 33.33MHz
AGP = 66.66MHz
VDDL
IOAPIC
GND
X1
X2
VDD
**FS0/REF0
VDD
**FS1/AGP0
AGP1
GND
*FS2/PCICLK_F
PCICLK0
PCICLK1
PCICLK2
GND
VDD
*MODE/PCICLK3
PCICLK4
*(PD#)PCICLK5
VDD
**FS3/48MHz
GND
SCLK
1
GND
CPUCLK0
CPUCLK1
VDDL
SDATA
SDRAM0
SDRAM1
GND
VDD
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDD
GND
SDRAM6
SDRAM7
SDRAM8
SDRAM9
GND
VDD
SDRAM10(PCI_STOP#)*
SDRAM11(CPU_STOP#)*
SDRAM12(PD#)*
ICS9248-172
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Advance Information
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
FS3
FS2
FS1
FS0
CPU
SDRAM
0
66.66
0
1
66.66
100.00
0
1
0
100.00
66.66
0
1
100.00
0
1
0
100.00
133.33
0
1
0
1
133.33
66.66
0
1
0
133.33
100.00
0
1
133.33
1
0
66.66
1
0
1
66.66
100.00
1
0
1
0
100.00
66.66
1
0
1
100.00
1
0
100.00
133.33
1
0
1
133.33
66.66
1
0
133.33
100.00
1
133.33
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| ICS9248YF-172LF-T | 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
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| ICS9248YF-179LF-T | 166.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9248YF-179-T | 166.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9248YF-179-T | 166.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
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