參數(shù)資料
型號: ICS9150-08
英文描述: Frequency Generator & Integrated Buffers for Pentium/Pro⑩
中文描述: 頻率發(fā)生器
文件頁數(shù): 8/14頁
文件大?。?/td> 329K
代理商: ICS9150-08
8
ICS9150-01
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the
ICS9150-01
. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is
100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped
in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than
4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs
inside the
ICS9150-01.
3. All other clocks continue to run undisturbed.
4. PCI_STOP# is shown in a high (true) state.
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