- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄8707 > ICS8S89834AKILFT (IDT, Integrated Device Technology Inc)IC CLOCK MUX 2:4 1GHZ 16-VFQFN PDF資料下載
參數(shù)資料
| 型號(hào)： | ICS8S89834AKILFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 2/17頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CLOCK MUX 2:4 1GHZ 16-VFQFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | HiPerClockS™ |
| 類型： | 多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 輸入： | LVCMOS，LVTTL |
| 輸出： | ECL，LVPECL |
| 頻率 - 最大： | 1GHz |
| 電源電壓： | 2.375 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 16-VFQFPN（3x3） |
| 包裝： | 帶卷 (TR) |
第1頁(yè)當(dāng)前第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)
ICS8S89834I Data Sheet
LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER
ICS8S89834AKI REVISION A FEBRUARY 4, 2010
10
2010 Integrated Device Technology, Inc.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 3A and 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 3A. 3.3V LVPECL Output Termination
Figure 3B. 3.3V LVPECL Output Termination
3.3V
V
CC - 2V
R1
50
R2
50
RTT
Z
o = 50
Z
o = 50
+
_
RTT =
* Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
LVPECL
Input
R1
84
R2
84
3.3V
R3
125
R4
125
Z
o = 50
Z
o = 50
LVPECL
Input
3.3V
+
_
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC2612CMS8#TR | IC DAC 14BIT DUAL R-R VOUT 8MSOP |
| CY2SSTV850ZCT | IC PLL BUF/DRIV I2C 1:10 48TSSOP |
| AD5320BRT-500RL7 | IC DAC 12BIT R-R W/BUFF SOT23-6 |
| VE-JNK-MY | CONVERTER MOD DC/DC 40V 50W |
| VE-JNJ-MY | CONVERTER MOD DC/DC 36V 50W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS8S89875AKILF | 制造商:Integrated Device Technology Inc 功能描述:IC CLK MULTPLX 1:2 2.5GHZ 16VFQF |
| ICS8S89875AKILFT | 制造商:Integrated Device Technology Inc 功能描述:IC CLK MULTPLX 1:2 2.5GHZ 16VFQF |
| ICS90C61A-PR2M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS90C61A-PR2N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS90C61A-PR2V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。