參數(shù)資料
型號: ICS8S89834AKILFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 13/17頁
文件大?。?/td> 0K
描述: IC CLOCK MUX 2:4 1GHZ 16-VFQFN
標(biāo)準(zhǔn)包裝: 2,500
系列: HiPerClockS™
類型: 多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 2:4
差分 - 輸入:輸出: 無/是
輸入: LVCMOS,LVTTL
輸出: ECL,LVPECL
頻率 - 最大: 1GHz
電源電壓: 2.375 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-VFQFPN(3x3)
包裝: 帶卷 (TR)
ICS8S89834I Data Sheet
LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER
ICS8S89834AKI REVISION A FEBRUARY 4, 2010
5
2010 Integrated Device Technology, Inc.
Table 4D. LVPECL DC Characteristics, VCC = 3.3V ± 10% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
NOTE 1: Outputs terminated with 50
to V
CC - 2V.
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = 2.5V ± 5% or or 3.3V ± 10%, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
All parameters are measured at
≤ 1GHz unless otherwise noted.
NOTE 1: Measured from VCC/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOH
Output High Voltage; NOTE 1
VCC – 1.145
VCC – 0.80
V
VOL
Output Low Voltage; NOTE 1
VCC – 1.945
VCC – 1.60
V
VOUT
Output Voltage Swing
0.6
1.0
V
VDIFF_OUT Differential Output Voltage Swing
1.2
2.0
V
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Maximum Frequency
1GHz
tPLH
Propagation Delay; Low-to-High; NOTE 1
250
550
ps
tPHL
Propagation Delay; High-to-Low; NOTE 1
300
550
ps
tSW
Switchover Time
SEL to Q
300
550
ps
tsk(o)
Output Skew; NOTE 2, 3
30
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
100
ps
tjit
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
200MHz
Integration Range:
(12kHz - 20MHz)
0.12
ps
tS
Clock Enable Setup Time
EN to IN1, IN2
300
ps
tH
Clock Enable Hold Time
EN to IN1, IN2
500
ps
tR / tF
Output Rise/Fall Time
20% to 80%
50
250
ps
odc
Output Duty Cycle
fMAX < 622MHz
48
52
%
fMAX ≥ 622MHz
45
55
%
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