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參數(shù)資料
| 型號(hào)： | ICS8752YT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大小： | 105K |
| 代理商： | ICS8752YT |
8752
www.icst.com
REV. A FEBRUARY 20, 2001
1
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
PRELIMINARY
BLOCK DIAGRAM
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
QB1
QB0
VDDO
QA3
QA2
GND
DIV_SELB0
DIV_SELB1
DIV_SELA0
DIV_SELA1
MR/nOE
REF_CLK1
GND
FB_IN
VDDO
QA1
QA0
GND
REF_CLK2
VDDI
VDDA
CLK_SEL
VDDO
QB2
QB3
GND
nc
PLL_SEL
VDDI
ICS8752
32-Lead LQFP
Y package
Top View
÷2
÷4
÷6
÷8
÷12
PLL
PHASE
DETECTOR
PLL_SEL
FB_IN
REF_CLK1
REF_CLK2
REF_SEL
DIV_SELA1
DIV_SELA0
DIV_SELB1
DIV_SELB0
MR/nOE
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
0
1
0
00
01
10
11
00
01
10
11
VCO
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
GENERAL DESCRIPTION
The ICS8752 is a low voltage, low skew clock
generator and a member of the HiPerClockS
family of High Performance Clock Solutions
from ICS. With output frequencies up to 250MHz
the ICS8752 is targeted for high performance
clock applications. Along with a fully integrated PLL the
ICS8752 contains frequency configurable outputs and an
external feedback input for regenerating clocks with “zero de-
lay”.
Dual clock inputs, REF_CLK1 and REF_CLK2, support
redundant clock applications. The CLK_SEL input determines
which reference clock is used. The output divider values of
Bank A and B are controlled by the DIV_SELA0:1, and
DIV_SELB0:1, respectively.
For test and system debug purposes the PLL_SEL input
allows the PLL to be bypassed. When HIGH the MR/nOE
input resets the internal dividers and forces the outputs to
the high impedance state.
The low impedance LVCMOS outputs of the ICS8752 are
designed to drive terminated transmission lines. The effec-
tive fanout of each output can be doubled by utilizing the
ability of each output to drive two series terminated trans-
mission lines.
FEATURES
Fully integrated PLL
8 LVCMOS outputs, 7 typical output impedance
External feedback for ”zero delay” clock regeneration
Output frequency up to 250MHz
Dual LVCMOS clock inputs for redundant clock applications
LVCMOS control inputs
Bank skew, tsk(b), 350ps
Output skew, tsk(o), 450ps
Multiple-frequency skew, tsk(w), 550ps
Cycle-to-cycle jitter, tjit(cc), ±100ps, typical
PLL reference zero delay, t(), ±100ps
Full 3.3V
32 lead low-profile QFP(LQFP)
7mm x 7mm x 1.4mm package body, 0.8mm lead pitch
0°C to 70°C ambient operating temperature
Functionally compatible with the MPC952 in some applications
Industrial temperature versions available upon request
HiPerClockS
,&6
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