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參數(shù)資料
| 型號(hào)： | ICS87946AYI-147LF |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, LQFP-32 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 127K |
| 代理商： | ICS87946AYI-147LF |
87946AYI-147
www.icst.com/products/hiperclocks.html
REV. A APRIL 21, 2003
1
Integrated
Circuit
Systems, Inc.
ICS87946I-147
LOW SKEW,
÷1, ÷2
LVCMOS/LVTTL CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87946I-147 is a low skew, ÷1, ÷2
LVCMOS/LVTTL Clock Generator and a member
of the HiPerClockS family of High Performance
Clock Solutions from ICS. The ICS87946I-147 has
two selectable single ended clock inputs. The single
ended clock inputs accept LVCMOS or LVTTL input levels. The
low impedance LVCMOS/LVTTL outputs are designed to drive
50
series or parallel terminated transmission lines. The effec-
tive fanout can be increased from 10 to 20 by utilizing the ability
of the outputs to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The master reset
input, MR/nOE, resets the internal frequency dividers and also
controls the active and high impedance states of all outputs.
The ICS87946I-147 is characterized at full 3.3V for input V
DD,
and mixed 3.3V and 2.5V for output operating supply mode. Guar-
anteed bank, output and part-to-part skew characteristics make
the ICS87946I-147 ideal for those clock distribution applications
demanding well defined performance and repeatability.
FEATURES
10 single ended LVCMOS/LVTTL outputs,
7
typical output impedance
Selectable CLK0 and CLK1 LVCMOS/LVTTL clock inputs
CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
Maximum output frequency: 250MHz
Bank skew: 30ps (maximum)
Output skew: 175ps (maximum)
Part-to-part skew: 850ps (maximum)
Multiple frequency skew: 200ps (maximum)
3.3V input, outputs may be either 3.3V or 2.5V supply
-40°C to 85°C ambient operating temperature
Pin compatible to the MPC9446 and MPC946
DIV_SELA
DIV_SELB
DIV_SELC
MR/nOE
QA0:QA2
QB0:QB2
QC0:QC3
CLK_SEL
CLK0
CLK1
32-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
Top View
HiPerClockS
,&6
0
1
÷1
÷2
0
1
0
1
0
1
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
QB0
VDDB
QB1
GND
QB2
VDDB
VDDC
CLK_SEL
VDD
CLK0
CLK1
DIV_SELA
DIV_SELB
DIV_SELC
GND
QC3
GND
QC2
V
DDC
QC1
GND
QC0
V
DDC
V
DDA
QA2
GND
QA1
V
DDA
QA0
GND
MR/nOE
ICS87946I-147
-
.
-
BLOCK DIAGRAM
PIN ASSIGNMENT
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS87946AYI-147LFT | 功能描述:IC CLOCK GENERATOR 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS87946AYI-147T | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK DIVIDER 32LQFP |
| ICS87946AYILF | 功能描述:IC CLK GEN LVCMOS /1 /2 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ICS87946AYILFT | 功能描述:IC CLOCK GENERATOR 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS87949AYI | 制造商:ICS 功能描述: |
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