參數(shù)資料
型號: ICS87946AY
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
文件頁數(shù): 1/9頁
文件大?。?/td> 131K
代理商: ICS87946AY
87946AY
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2002
1
Integrated
Circuit
Systems, Inc.
ICS87946
LOW SKEW,
÷1, ÷2
LVCMOS CLOCK GENERATOR
PRELIMINARY
GENERAL DESCRIPTION
The ICS87946 is a low skew, ÷1, ÷2 LVCMOS
Clock Generator and a member of the
HiPerClockS family of High Performance Clock
Solutions from ICS. The ICS87946 has two se-
lectable single ended clock inputs. The single
ended clock inputs accept LVCMOS or LVTTL input levels.
The low impedance LVCMOS outputs are designed to drive
50
series or parallel terminated transmission lines. The ef-
fective fanout can be increased from 10 to 20 by utilizing the
ability of the outputs to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The master reset
input, MR/nOE, resets the internal frequency dividers and also
controls the active and high impedance states of all outputs.
The ICS87946 is characterized at 3.3V core/3.3V output.
Guaranteed output and part-to-part skew characteristics
make the ICS87946 ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
FEATURES
10 single ended LVCMOS outputs, 7
typical output
impedance
Selectable CLK0 and CLK1 LVCMOS clock inputs
CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
Maximum input frequency: 250MHz
Output skew: 350ps (maximum)
3.3V input, 3.3V outputs
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
Pin compatible to the MPC946
BLOCK DIAGRAM
PIN ASSIGNMENT
DIV_SELA
DIV_SELB
DIV_SELC
MR/nOE
QA0 - QA2
QB0 - QB2
QC0 - QC3
CLK_SEL
CLK0
CLK1
32-Lead LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
HiPerClockS
,&6
0
1
÷1
÷2
0
1
0
1
0
1
32 31 30 29 28 27 26 25
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
QB0
VDDB
QB1
GND
QB2
VDDB
VDDC
CLK_SEL
VDD
CLK0
CLK1
DIV_SELA
DIV_SELB
DIV_SELC
GND
QC3
GND
QC2
V
DDC
QC1
GND
QC0
V
DDC
V
DDA
QA2
GND
QA1
V
DDA
QA0
GND
MR/nOE
ICS87946
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
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