參數(shù)資料
型號: ICS8431AMI-21LF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產生/分配
英文描述: 350 MHz, OTHER CLOCK GENERATOR, PDSO28
封裝: 7.50 X 18.05 MM, 2.25 MM HEIGHT, ROHS COMPLIANT, MS-013, MO-119, SOIC-28
文件頁數(shù): 1/16頁
文件大?。?/td> 256K
代理商: ICS8431AMI-21LF
8431AMI-21
www.icst.com/products/hiperclocks.html
REV. A AUGUST 2, 2005
1
Integrated
Circuit
Systems, Inc.
ICS8431I-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-
TO
-3.3V LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS8431I-21 is a general purpose clock fre-
quency synthesizer for IA64/32 application and a
member of the HiPerClockS family of High Per-
formance Clock Solutions from ICS. The VCO op-
erates at a frequency range of 250MHz to 700MHz
providing an output frequency range of 62.5MHz to 350MHz.
The output frequency can be programmed using the parallel in-
terface, M0 through M8 to the configuration logic, and the output
divider control pin, DIV_SEL. Spread spectrum clocking is pro-
grammed via the control inputs SSC_CTL0 and SSC_CTL1.
Programmable features of the ICS8431I-21 support four op-
erational modes. The four modes are spread spectrum clock-
ing (SSC), non-spread spectrum clock and two test modes
which are controlled by the SSC_CTL[1:0] pins. Unlike other
synthesizers, the ICS8431I-21 can immediately change
spread-spectrum operation without having to reset the device.
In SSC mode, the output clock is modulated in order to achieve
a reduction in EMI. In one of the PLL bypass test modes, the
PLL is disconnected as the source to the differential output
allowing an external source to be connected to the TEST_I/O
pin. This is useful for in-circuit testing and allows the differen-
tial output to be driven at a lower frequency throughout the
system clock tree. In the other PLL bypass mode, the oscilla-
tor divider is used as the source to both the M and the Fout
divide by 2. This is useful for characterizing the oscillator and
internal dividers.
XTAL_IN
XTAL_OUT
M0:M8
PLL
FOUT
nFOUT
÷ 16
TEST_I/O
OSC
VCO
÷2
÷4
PHASE
DETECTOR
÷ M
SSC
Control
Logic
Configuration
Logic
nP_LOAD
SSC_CTL0
FEATURES
Fully integrated PLL
Differential 3.3V LVPECL output
Crystal oscillator interface
Output frequency range: 62.5MHz to 350MHz
Crystal input frequency range: 14MHz to 25MHz
VCO range: 250MHz to 700MHz
Programmable PLL loop divider for generating a variety
of output frequencies
Spread Spectrum Clocking (SSC) fixed at 1/2% modulation
for environments requiring ultra low EMI
PLL bypass modes supporting in-circuit testing and on-chip
functional block characterization
Cycle-to-cycle jitter: 30ps (maximum)
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Replaces ICS8431I-01
Available in both, Standard and RoHS/Lead-Free
compliant packages
BLOCK DIAGRAM
PIN ASSIGNMENT
SSC_CTL1
M0
M1
M2
M3
M4
M5
M6
M7
M8
SSC_CTL0
SSC_CTL1
VEE
TEST_I/O
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nP_LOAD
VCC
XTAL_IN
XTAL_OUT
nc
VCCA
VEE
MR
DIV_SEL
VCCO
FOUT
nFOUT
VEE
ICS8431I-21
28-Lead SOIC
7.5mm x 18.05mm x 2.25mm package body
M Package
Top View
DIV_SEL
HiPerClockS
ICS
相關PDF資料
PDF描述
ICS8431CM-01LF 200 MHz, OTHER CLOCK GENERATOR, PDSO28
ICS8431CM-11T 255 MHz, OTHER CLOCK GENERATOR, PDSO28
ICS8431CM-11LFT 255 MHz, OTHER CLOCK GENERATOR, PDSO28
ICS8431DMI-01 200 MHz, OTHER CLOCK GENERATOR, PDSO28
ICS8431DMI-01LFT 200 MHz, OTHER CLOCK GENERATOR, PDSO28
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