參數(shù)資料
型號: ICS8422002AGILFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 9/16頁
文件大?。?/td> 0K
描述: IC SYNTHESIZER LVHSTL 20-TSSOP
標準包裝: 2,500
系列: HiPerClockS™, FemtoClock™
類型: 頻率合成器
PLL: 帶旁路
輸入: LVCMOS,LVTTL,晶體
輸出: LVHSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 226.66MHz
除法器/乘法器: 是/是
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 20-TSSOP
包裝: 帶卷 (TR)
其它名稱: 8422002AGILFT
ICS8422002AGI REVISION A AUGUST 12, 2009
2
2009 Integrated Device Technology, Inc.
ICS8422002I Data Sheet
FEMTOCLOCK CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number
Name
Type
Description
1, 7
nc
Unused
No connect.
2, 20
VDDO
Power
Output supply pins.
3, 4
Q0, nQ0
Output
Differential output pair. LVHSTL interface levels.
5
MR
Input
Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
6
nPLL_SEL
Input
Pulldown
PLL select control. When LOW, the selected reference clock is
frequency-multiplied by the PLL. When HIGH, the PLL is bypassed and the
selected reference clock is routed directly to the output dividers.
LVCMOS/LVTTL interface levels.
8VDDA
Power
Analog supply pin.
9, 11
F_SEL0,
F_SEL1
Input
Pulldown
Frequency select pins. LVCMOS/LVTTL interface levels.
10, 16
VDD
Power
Core supply pins.
12, 13
XTAL_OUT,
XTAL_IN
Input
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
14
REF_CLK
Input
Pulldown
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
15
nXTAL_SEL
Input
Pulldown
Selects between crystal or REF_CLK inputs as the PLL Reference source.
Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
17
GND
Power
Power supply ground.
18, 19
nQ1, Q1
Output
Differential output pair. LVHSTL interface levels.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4pF
RPULLDOWN Input Pulldown Resistor
51
k
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