參數(shù)資料
型號: ICS8421002AGILFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/15頁
文件大小: 0K
描述: IC FREQ SYNTHESIZER 20-TSSOP
標準包裝: 2,500
系列: HiPerClockS™, FemtoClock™
類型: 頻率合成器
PLL: 帶旁路
輸入: LVCMOS,LVTTL,晶體
輸出: LVHSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 226.66MHz
除法器/乘法器: 是/無
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
其它名稱: 8421002AGILFT
FEMTOCLOCKS CRYSTAL-TO-HSTL
FREQUENCY SYNTHESIZER
ICS8421002I
IDT / ICS HSTL FREQUENCY SYNTHESIZER
1
ICS8421002I REV B
MARCH 02, 2009
GENERAL DESCRIPTION
The ICS8421002I is a 2 output HSTL Synthesizer
optimized to generate Fibre Channel reference clock
frequencies and is a member of the HiPerClocksTM
family of high performance clock solutions from IDT.
Using a 26.5625MHz 18pF parallel resonant crystal,
the following frequencies can be generated based on the 2
frequency select pins (F_SEL[1:0]): 212.5MHz, 187.5MHz,
159.375MHz, 106.25MHz and 53.125MHz. The ICS8421002I uses
IDT’s 3rd generation low phase noise VCO technology and can
achieve 1ps or lower typical rms phase jitter, easily meeting Fibre
Channel jitter requirements. The ICS8421002I is packaged in a
small 20-pin TSSOP package.
FEATURES
Two HSTL outputs (VOHmax = 1.5V)
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 106.25MHz, 53.125MHz
VCO range: 560MHz - 680MHz
RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.59ps (typical)
Power supply modes:
Core/Output
3.3V/1.8V
2.5V/1.8V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) an lead-free (RoHS 6)
packages
HiPerClockS
ICS
1
0
1
0
Phase
Detector
VCO
M = 24 (fixed)
F_SEL[1:0]
0 0
÷3 (default)
0 1
÷4
1 0
÷6
1 1
÷12
2
OSC
BLOCK DIAGRAM
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FREQUENCY SELECT FUNCTION TABLE
F_SEL[1:0]
nPLL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
nXTAL_SEL
MR
Q0
nQ0
Q1
nQ1
Pulldown
26.5625MHz
Pulldown
ICS8421002I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
nc
VDDO
Q0
nQ0
MR
nPLL_SEL
nc
VDDA
F_SEL0
VDD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDDO
Q1
nQ1
GND
VDD
nXTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
F_SEL1
PIN ASSIGNMENT
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