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參數(shù)資料
| 型號(hào)： | ICS8421002AGILFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 14/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FREQ SYNTHESIZER 20-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | HiPerClockS™, FemtoClock™ |
| 類型： | 頻率合成器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | LVHSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 226.66MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 8421002AGILFT |
IDT / ICS HSTL FREQUENCY SYNTHESIZER
8
ICS8421002I REV B MARCH 02, 2009
ICS8421002I
FEMTOCLOCKS CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
CRYSTAL INPUT INTERFACE
The ICS8421002I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in
Figure 2 below
Figure 2. CRYSTAL INPUt INTERFACE
were determined using a 26.5625MHz 18pF parallel resonant
crystal and were chosen to minimize the ppm error.
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8421002I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance, power
supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10
V
DDA
10
F
.01
F
3.3V or 2.5V
.01
F
V
DD
C1
22p
X1
18pF Parallel Crystal
C2
22p
XTAL_OUT
XTAL_IN
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k
resistor can be tied
from XTAL_IN to ground.
REF_CLK INPUT:
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1k
resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
HSTL OUTPUT
All unused HSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
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相關(guān)代理商/技術(shù)參數(shù) |
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| ICS8421002AGIT | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER |
| ICS8421002AI | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER |
| ICS8421002I | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER |
| ICS8421002I-01 | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER |
| ICS8421004AGI | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS? CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER |
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