參數(shù)資料
型號: ICS8422002AGILFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 16/16頁
文件大小: 0K
描述: IC SYNTHESIZER LVHSTL 20-TSSOP
標準包裝: 2,500
系列: HiPerClockS™, FemtoClock™
類型: 頻率合成器
PLL: 帶旁路
輸入: LVCMOS,LVTTL,晶體
輸出: LVHSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 226.66MHz
除法器/乘法器: 是/是
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 20-TSSOP
包裝: 帶卷 (TR)
其它名稱: 8422002AGILFT
ICS8422002AGI REVISION A AUGUST 12, 2009
9
2009 Integrated Device Technology, Inc.
ICS8422002I Data Sheet
FEMTOCLOCK CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Crystal Input Interface
The ICS8422002I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2 below
were determined using a 26.5625MHz 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The input
edge rate can be as slow as 10ns. For LVCMOS signals, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the crystal input will attenuate the signal in half. This can be done in
one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50
applications, R1 and R2
can be 100
. This can also be accomplished by removing R1 and
making R2 50
. By overdriving the crystal oscillator, the device will
be functional, but note the device performance is guaranteed by
using a quartz crystal.
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
22p
C2
22p
XTAL_IN
XTAL_OUT
Ro
Rs
Zo = Ro + Rs
50
0.1f
R1
R2
VDD
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