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參數(shù)資料
| 型號(hào)： | ICS841S012DKILFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 5/23頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FREQ SYNTHESIZER 56VFQFN |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | HiPerClockS™, PCI Express® (PCIe) |
| 類型： | 時(shí)鐘/頻率合成器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | PCI Express（PCIe） |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12 |
| 差分 - 輸入:輸出： | 是/無(wú) |
| 頻率 - 最大： | 250MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 56-VFQFP-EP（8x8） |
| 包裝： | 帶卷 (TR) |
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ICS841S012BKI REVISION A NOVEMBER 10, 2009
13
2009 Integrated Device Technology, Inc.
ICS841S012I Data Sheet
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER
FIGURE 5. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
VFQFN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package
and the electr ical perfor mance, a land patter n must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in
Figure 5. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”)
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the
Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor
Technology.
THERMAL VIA
LAND PATTERN
SOLDER
PIN
SOLDER
PIN PAD
PIN
GROUND PLANE
EXPOSED HEAT SLUG
(GROUND PAD)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS841S012I | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Crystal-to-0.7V Differential HCSL/LVCMOS Frequency Synthesizer |
| ICS841S01BG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PCI EXPRESS⑩ CLOCK GENERATOR |
| ICS841S01BGLF | 功能描述:IC CLK GENERATOR PLL 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:HiPerClockS™, PCI Express® (PCIe) 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| ICS841S01BGLFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PCI EXPRESS⑩ CLOCK GENERATOR |
| ICS841S01BGT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PCI EXPRESS⑩ CLOCK GENERATOR |
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