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參數(shù)資料
型號: ICS81006AKLF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 3/17頁
文件大?。?/td> 0K
描述: IC VCXO LOW PHASE NOISE 20-VFQFN
標準包裝: 75
系列: HiPerClockS™
類型: 壓控晶體振蕩器(VCXO)
PLL:
輸入: 晶體
輸出: LVCMOS,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 1:6
差分 - 輸入:輸出: 無/無
頻率 - 最大: 31.25MHz
除法器/乘法器: 是/無
電源電壓: 1.6 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 20-VFQFPN(4x4)
包裝: 管件
其它名稱: 800-1099
800-1099-5
800-1099-ND
81006AKLF
IDT / ICS VCXO-TO-LVCMOS OUTPUTS
11
ICS81006AK REV. B OCTOBER 8, 2008
ICS81006
VCXO-TO-6 LVCMOS OUTPUTS
SCHEMATIC EXAMPLE
Figure 2 shows an example of ICS81006I application schematic.
The decoupling capacitors should be located as close as
possible to the power pin. For the LVCMOS 20
Ω output drivers,
series termination example is shown in the schematic. Additional
termination approaches are shown in the LVCMOS Termination
Application Note.
FIGURE 2. ICS81006I SCHEMATIC EXAMPLE
INPUTS:
CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω resistor can be used. The VC pin can not be
floated.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
C2
SPARE
R5
1K
VC = 0V to VDD
VDD
C1
SPARE
U1
81006
2
3
4
5
6
7
8
9
11
12
13
14
17
18
19
20
10
16
15
1
XTAL_OUT
VDD
VC
DIV_SEL_Q5
OE
1
GN
D
Q5
VD
D
O
GND
Q3
VDDO
Q2
VD
D
O
Q0
GN
D
OE
0
Q4
Q
1
GND
XTAL_IN
Zo = 50
(U1-13)
C3
0.1uF
Unused outputs can be left floating. There should be
no trace attached to unused outputs. Device
characterized and specification limits set with all
outputs terminated.
C6
0.1uF
C5
0.1uF
C7
10uf
Pull-up
example
(U1-9)
R4
1K
Quartz crystal should be
placed as close to the
device as possible.
VDDO
Pull-down
example
VDD
R3
1K
VDDO
R1
30
VDD
R2
30
VC
C4
0.1uF
XTAL
(U1-17)
Zo = 50
VDD
(U1-3)
81006I
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