IDT / ICS VCXO-TO-LVCMOS OUTPUTS 1" />
參數(shù)資料
型號: ICS81006AKLF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 2/17頁
文件大?。?/td> 0K
描述: IC VCXO LOW PHASE NOISE 20-VFQFN
標準包裝: 75
系列: HiPerClockS™
類型: 壓控晶體振蕩器(VCXO)
PLL:
輸入: 晶體
輸出: LVCMOS,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 1:6
差分 - 輸入:輸出: 無/無
頻率 - 最大: 31.25MHz
除法器/乘法器: 是/無
電源電壓: 1.6 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤
供應商設(shè)備封裝: 20-VFQFPN(4x4)
包裝: 管件
其它名稱: 800-1099
800-1099-5
800-1099-ND
81006AKLF
IDT / ICS VCXO-TO-LVCMOS OUTPUTS
10
ICS81006AK REV. B OCTOBER 8, 2008
ICS81006
VCXO-TO-6 LVCMOS OUTPUTS
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.
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TABLE 6. VARACTOR PARAMETERS
FORMULAS
(
) (
)
() (
)
Low
V
S
L
Low
V
S
L
Low
V
S
L
Low
V
S
L
Low
C
_
2
_
1
_
2
_
1
+
+
=
(
) (
)
() (
)
High
V
S
L
High
V
S
L
High
V
S
L
High
V
S
L
High
C
_
2
_
1
_
2
_
1
+
+
=
6
0
1
0
1
0
10
1
2
1
2
1
)
(
+
+
=
C
TPR
Range
Pull
Total
High
Low
C
Low
is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance.
C
Low
determines the high frequency component on the TPR.
C
High
is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance.
C
High
determines the low frequency component on the TPR.
Absolute Pull Range (APR) = Total Pull Range – (Frequency Tolerance + Frequency Stability + Aging)
EXAMPLE CALCULATIONS
Using the tables and figures above, we can now calculate the
TPR and APR of the VCXO using the example crystal parameters.
For the numerical example below there were some assumptions
made. First, the stray capacitance (C
S1, CS2), which is all the excess
capacitance due to board parasitic, is 4pF. Second, the expected
lifetime of the project is 5 years; hence the inaccuracy due to
aging is ±15ppm. Third, though many boards will not require load
tuning capacitors (C
L1, CL2), it is recommended for long-term
consistent performance of the system that two tuning capacitor
pads be placed into every design. Typical values for the load tuning
capacitors will range from 0 to 4pF.
() ()
pf
C
Low
7
.
9
4
.
15
4
0
4
.
15
4
0
4
.
15
4
0
4
.
15
4
0
=
+
+
=
() ()
() (
)
pf
C
High
8
.
16
6
.
29
4
0
6
.
29
4
0
6
.
29
4
0
6
.
29
4
0
=
+
+
=
ppm
pF
TPR
5
.
226
10
4
8
.
16
1
220
2
1
4
7
.
9
1
220
2
1
6
=
+
+
=
TPR = ±113.25ppm
APR = 113.25ppm – (20ppm + 20ppm + 15ppm) = ±58.25ppm
The example above will ensure a total pull range of
±113.25 ppm with an APR of ±58.25ppm. Many times, board
designers may select their own cr ystal based on their
application. If the application requires a tighter APR, a crystal
with better pullability (C0/C1 ratio) can be used. Also, with the
equations above, one can var y the frequency tolerance,
temperature stability, and aging or shunt capacitance to achieve
the required pullability.
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