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參數(shù)資料
| 型號： | ICS6953BI147 |
| 英文描述： | DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER |
| 中文描述： | 差分至的LVCMOS / LVTTL零延遲緩沖器 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 265K |
| 代理商： | ICS6953BI147 |
86953BYI-147
www.icst.com/products/hiperclocks.html
REV. B APRIL 23, 2004
8
Integrated
Circuit
Systems, Inc.
ICS86953I-147
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVCMOS / LVTTL Z
ERO
D
ELAY
B
UFFER
VDD
(U1-23)
Zo = 50 Ohm
1R7
R4
50
0C2
0C11
R1
36
VDD
0C5
R3
50
R9
1K
R8
1K
0C4
R5
50
C6 (Option)
0.1u
(U1-19)
(U1-27)
R2
36
Zo = 50
VCC
(U1-11)
R6
1K
0C3
LVPECL Driver
0C1
U1
ICS86953I-147
1
2
3
4
5
6
7
8
1
1
1
1
1
1
1
17
18
19
20
21
22
23
24
3
3
3
2
2
2
2
2
9
VDDA
FB_CLK
nc
nc
nc
nc
GND
PCLK
M
V
Q
G
Q
V
Q
GND
Q4
VDDO
Q3
GND
Q2
VDDO
Q1
V
n
P
G
Q
V
Q
G
n
Zo = 50
VDD
Zo = 50 Ohm
C16
10u
(U1-15)
VDD
R10
1K
L
AYOUT
G
UIDELINE
The schematic of the ICS86953I-147 layout example is shown in
Figure 4A.The ICS86953I-147 recommended PCB board layout
for this example is shown in Figure 4B. This layout example is
used as a general guideline. The layout in the actual system will
depend on the selected component types, the density of the
components, the density of the traces, and the stack up of the
P.C. board.
F
IGURE
4A. ICS86953I-147 LVCMOS Z
ERO
D
ELAY
B
UFFER
S
CHEMATIC
E
XAMPLE
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