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參數(shù)資料
| 型號(hào)： | ICS6953BI147 |
| 英文描述： | DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER |
| 中文描述： | 差分至的LVCMOS / LVTTL零延遲緩沖器 |
| 文件頁(yè)數(shù)： | 7/13頁(yè) |
| 文件大?。?/td> | 265K |
| 代理商： | ICS6953BI147 |
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86953BYI-147
www.icst.com/products/hiperclocks.html
REV. B APRIL 23, 2004
7
Integrated
Circuit
Systems, Inc.
ICS86953I-147
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVCMOS / LVTTL Z
ERO
D
ELAY
B
UFFER
PCLK/nPCLK C
LOCK
I
NPUT
I
NTERFACE
The PCLK/nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
and V
must meet the V
PP
and V
input requirements. Figures 3A to 3D show inter-
face examples for the HiPerClockS PCLK/nPCLK input driven
by the most common driver types. The input interfaces sug-
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
F
IGURE
3A. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
A
CML D
RIVER
F
IGURE
3B. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
AN
SSTL
IN
D
RIVER
F
IGURE
3C. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
F
IGURE
3D. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
A
3.3V LVDS D
RIVER
PCLK/nPCLK
PCLK
nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
C2
R2
1K
R5
100
Zo = 50 Ohm
3.3V
3.3V
C1
R3
1K
LVDS
R4
1K
HiPerClockS
PCLK/nPCLK
PCLK
nPCLK
R1
1K
Zo = 50 Ohm
3.3V
3.3V
HiPerClockS
Input
PCLK
nPCLK
R2
84
R3
125
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
3.3V
Zo = 50 Ohm
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