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參數(shù)資料
| 型號： | ICS6953BI147 |
| 英文描述： | DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER |
| 中文描述： | 差分至的LVCMOS / LVTTL零延遲緩沖器 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 265K |
| 代理商： | ICS6953BI147 |
86953BYI-147
www.icst.com/products/hiperclocks.html
REV. B APRIL 23, 2004
1
Integrated
Circuit
Systems, Inc.
ICS86953I-147
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVCMOS / LVTTL Z
ERO
D
ELAY
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS86953I-147 is a low voltage, low skew
1-to-9 Differential-to-LVCMOS/LVTTL Clock
Generator and a member of the
HiPerClockS
family of High Performance Clock Solutions from
ICS. The PCLK, nPCLK pair can accept most stan-
dard differential input levels. With output frequencies up to 175MHz,
the ICS86953I-147 is targeted for high performance clock ap-
plications. Along with a fully integrated PLL, the ICS86953I-147
contains frequency configurable outputs and an external feed-
back input for regenerating clocks with “zero delay”.
F
EATURES
9 single ended LVCMOS/LVTTL outputs;
(8) clocks, (1) feedback
PCLK, nPCLK pair can accept the following differential
input levels: LVPECL, CML, SSTL
Maximum output frequency: PLL Mode, 175MHz
VCO range: 250MHz to 700MHz
Output skew: 75ps (maximum)
Cycle-to-cycle jitter: 50ps (maximum)
Static phase offset: 90ps ± 110ps
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Pin compatible to the MPC953
B
LOCK
D
IAGRAM
HiPerClockS
ICS
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
Q1
V
DDO
Q2
GND
Q3
V
DDO
Q4
GND
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
ICS86953I-147
Q
V
D
Q
G
Q
V
D
M
n
V
DDA
FB_CLK
nc
nc
nc
nc
GND
PCLK
G
Q
V
D
Q
G
P
n
V
P
IN
A
SSIGNMENT
Phase
Detector
LPF
VCO
÷2
÷4
0
1
0
1
PCLK
nPCLK
FB_CLK
VCO_SEL
nBYPASS
MR/nOE
PLL_SEL
QFB
Q0:Q6
Q7
7
/
0
1
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