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參數(shù)資料
| 型號(hào)： | ICS650-01B |
| 英文描述： | System Peripheral Clock Source |
| 中文描述： | 系統(tǒng)外部時(shí)鐘源 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 47K |
| 代理商： | ICS650-01B |
ICS650-01B
System Peripheral Clock Source
MDS 650-01B A
Integrated Circuit Systems 525 Race Street San Jose CA95126 (408) 295-9800tel (408) 295-9818fax
3
Revision 041499
Printed 11/15/00
Parameter
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage temperature
DC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
Operating Voltage, VDD
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH, VDD = 3.3 or 5V
Operating Supply Current, IDD, at 5V
Operating Supply Current, IDD, at 3.3V
Short Circuit Current, VDD = 3.3
Input Capacitance
AC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
Input Crystal or Clock Frequency
Output Clocks Accuracy (synthesis error)
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
One Sigma Jitter
One Sigma Jitter
Absolute Clock Period Jitter
Conditions
Minimum
Typical
Maximum
Units
Referenced to GND
Referenced to GND
7
V
V
°C
°C
°C
-0.5
0
VDD+0.5
70
260
150
Max of 10 seconds
-65
3.0
2
5.5
V
V
V
V
V
V
Select inputs, OE
Select inputs, OE
VDD=3.3V, IOH=-8mA
VDD=3.3V, IOL=8mA
IOH=-8mA
No Load, note 2
No Load, note 2
Each output
Except X1
0.8
2.4
0.4
VDD-0.4
50
25
±50
7
mA
mA
mA
pF
14.31818
MH z
ppm
ns
ns
%
ps
ps
ps
All clocks
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
Except ACLK
ACLK
PCLK, UCLK, BCLK
1
1.5
1.5
60
500
40
50
75
170
- 500
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With all clocks at highest frequencies.
External Components
The ICS650 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01μF should be connected between VDD and GND (on pins 4 and 6, and pins 16 and 14),
as close to the chip as possible. A series termination resistor of 33
may be used for each clock output. The
14.31818 MHz crystal must be connected as close to the chip as possible. The crystal should be a
fundamental mode, parallel resonant, 30 ppm or better (to meet the Ethernet specs). Crystal capacitors
should be connected from pins X1 to ground and X2 to ground. The value of these capacitors is given by
the following equation, where C
L
is the crystal load capacitance: Crystal caps (pF) = (C
L
-12) x 2. So for a
crystal with 16pF load capacitance, two 8pF caps should be used. If a clock input is used, drive it into X1
and leave X2 unconnected.
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