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參數(shù)資料
| 型號： | ICS650-01B |
| 英文描述： | System Peripheral Clock Source |
| 中文描述： | 系統(tǒng)外部時鐘源 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 47K |
| 代理商： | ICS650-01B |
ICS650-01B
System Peripheral Clock Source
MDS 650-01B A
Integrated Circuit Systems 525 Race Street San Jose CA95126 (408) 295-9800tel (408) 295-9818fax
2
Revision 041499
Printed 11/15/00
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
BSEL
X2
X1
VDD
GND
GND
BCLK1
BCLK2
ACLK
PCLK4
OE
PCLK1
14.318M
GND
ASEL
VDD
PCLK3
PCLK2
PSEL0
PSEL1
Type
I
XO
XI
P
P
P
O
O
O
O
I
O
O
P
I
P
O
O
I
I
Description
BCLK1 and BCLK2 Select pin. Determines frequency of B clocks per table above.
Crystal connection. Connect to parallel mode 14.31818 MHz crystal. Leave open for clock.
Crystal connection. Connect to parallel mode 14.31818 MHz crystal, or clock.
Connect to VDD. Must be same value as other VDD. Decouple with pin 6.
Connect to ground.
Connect to ground.
BCLK1 output. Determined by BSEL pin per table above.
BCLK2 output. Determined by BSEL pin per table above. Only clock active if PSEL1, 0=1.
AC97 Audio clock output per table above.
PCLK output number 4 per table above.
Output Enable. Tri-states all outputs when low.
PCLK output number 1 per table above.
14.31818 MHz buffered reference clock output.
Connect to ground.
ACLK Select pin. Determines frequency of Audio clock per table above.
Connect to VDD. Must be same value as other VDD. Decouple with pin 14.
PCLK output number 3 per table above.
PCLK output number 2 per table above.
Processor Select pin #0. Determines frequencies on PCLKs 1-4 per table above.
Processor Select pin #1. Determines frequencies on PCLKs 1-4 per table above.
Pin Descriptions
Key: I = Input; XO/XI = crystal connections; O = output; P = power supply connection
1
16
2
3
4
15
14
13
VDD
ACLK
X2
VDD
20 pin (150 mil) SSOP
5
6
7
8
12
11
10
9
PCLK4
PSEL0
X1
BSEL
PCLK2
PSEL1
PCLK3
PCLK1
OE
BCLK2
BCLK1
18
17
19
20
GND
GND
14.318M
GND
ASEL
PSEL1
0
0
0
M
M
M
1
1
1
PSEL0
0
M
1
0
M
1
0
M
1
PCLK1
25.00
TEST
TEST
40.00
33.3334
20.00
20.00
20.00
Stops low all clocks except BCLK2.
PCLK2,3
50.00
TEST
TEST
80.00
66.6667
40.00
33.3334
66.6667
PCLK4
18.75
TEST
TEST
20.00
25.00
25.00
25.00
25.00
Processor Clock (MHz)
BSEL
0
M
1
BCLK1
3.688
50
80
BCLK2
4.917
25
40
Audio Clock (MHz)
B Clocks (MHz)
0 = connect directly to ground, 1 = connect directly
to VDD, M=leave unconnected (floating)
Pin Assignment
ASEL
0
M
1
ACLK
49.152
24.576
12.288
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| ICS650R01I | System Peripheral Clock Source |
| ICS650-07B | Broadcom Clock Source |
| ICS650-07C | Networking Clock Source |
| ICS650-11B | BroadCom Networking Clock Synthesizer |
| ICS650R-11I | BroadCom Networking Clock Synthesizer |
相關代理商/技術參數(shù) |
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| ICS650-05 | 制造商:ICS 制造商全稱:ICS 功能描述:HDTV Clock Synthesizer |
| ICS650-07B | 制造商:ICS 制造商全稱:ICS 功能描述:Broadcom Clock Source |
| ICS650-07C | 制造商:ICS 制造商全稱:ICS 功能描述:Networking Clock Source |
| ICS650-11B | 制造商:ICS 制造商全稱:ICS 功能描述:BroadCom Networking Clock Synthesizer |
| ICS650-12 | 制造商:ICS 制造商全稱:ICS 功能描述:MPEG Clock Synthesizer |
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