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參數(shù)資料
| 型號(hào)： | ICS525RI-07 |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 250 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| 封裝： | 0.150 INCH, MO-153, SSOP-28 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 185K |
| 代理商： | ICS525RI-07 |
LVCMOS User Configurable Clock
MDS 525-07/08
B
5
Revision 031706
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS525-07/08
PRELIMINARY INFORMATION
External Components/Crystal
Selection
Decoupling Capacitors
The ICS525-07/08 require two 0.01F decoupling
capacitors to be connected between VDD and GND,
one on each side of the chip. The capacitor must be
connected close to the device to minimize lead
inductance.
Crystal Load Capacitors
The approximate total on-chip capacitance for a crystal
is 16 pF, so a parallel resonant, fundamental mode
crystal with this value of load (correlation) capacitance
should be used. For crystals with a specified load
capacitance greater than 16 pF, crystal capacitors may
be connected from each of the pins X1 and X2 to
Ground as shown in the block diagram. The value (in
pF) of these crystal caps should be (CL -16)*2, where
CL is the crystal load capacitance in pF. These external
capacitors are only required for applications where the
exact frequency is critical. For a clock input, connect to
X1 and leave X2 unconnected (no capacitors on
either).
Configuring the Frequency
The ICS525-07/08 output frequency is determined by
its internal dividers according to this equation:
V is the feedback divider and can be 8, 9, 10, 12...519
(not 11).
For the ICS525-07, R is the reference divider and can
be 2, 3, 4...129.
For the ICS525-08, R can be 1, 2...64.
For the ICS525-07, OD can be 1, 2, 3, 4, 5, 7, 12, or 16.
For the ICS525-08, OD can be 2, 3, 4, 5, 7, 8, 9, 10, 11,
13, 14, 15, 17, 19, 48, or 128.
The VCO must be kept in its operating range according
to this equation:
ICS525-07
ICS525-08
The phase detector must be kept in its operating range
according to this equation:
Optimum values for V, R, and OD are found iteratively
by applying the above equations. Choosing a smaller
value of R will give better jitter. A calculator program is
available on the ICS website to automate the process.
After determining V, R, and OD, convert them to the pin
address.
V8...0 = binary(V - 8)
Example: V = 17, V8...0 = 000001001
For the ICS525-07, R6...0 = binary(R - 2)
Example: R = 15, R6...0 = 0001101
For the ICS525-08, R5...0 - binary(R)
Example: R = 15, R5...0 = 001101
S2...0 or S3...0 is configured according to the tables on
page 4.
All of the configuration pins have on-chip pull-up
resistors, so pins can be floated to generate a “1”, or
tied to ground for a “0”. They can also be driven directly
by logic signals.
Output Termination
The output driver impedance is approximately 17
ohms. Use a 33 ohm series termination resistor on
each output to match a 50 ohm trace.
Reference Source
The initial accuracy and temperature stability of the
output frequency is determined by the reference
frequency source, the crystal, or the input clock. The
PLL will track the input frequency, so if the crystal is
running at +5 ppm the CLK frequency will also be +5
ppm. A low amplitude sinusoidal reference (such as the
1 V p-p signal from a TCXO) can be used by the AC
coupling it to the X1 pin with a 0.1 F capacitor. The X1
pin is self-biasing.
fOUT =
V * fIN
R * OD
V * fIN
R
75MHz
<
200MHz (1.8 V)
250MHz (2.5 V)
<
V * fIN
R
150MHz
<
400MHz (1.8 V)
500MHz (2.5 V)
<
fIN
R
250kHz
<
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| ICS525RI07LF | 制造商:ICS 制造商全稱:ICS 功能描述:LVCMOS User Configurable Clock |
| ICS525RI-07LF | 制造商:ICS 制造商全稱:ICS 功能描述:LVCMOS User Configurable Clock |
| ICS525RI-07LFT | 制造商:ICS 制造商全稱:ICS 功能描述:LVCMOS User Configurable Clock |
| ICS525RI-07T | 制造商:ICS 制造商全稱:ICS 功能描述:LVCMOS User Configurable Clock |
| ICS525RI-08 | 制造商:ICS 制造商全稱:ICS 功能描述:LVCMOS User Configurable Clock |
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