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| 型號(hào)： | ICS1893BFILFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 76/133頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | PHYceiver™ |
| 類型： | PHY 收發(fā)器 |
| 規(guī)程： | MII |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 1893BFILFT |
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Chapter 6 Functional Blocks
ICS1893BF, Rev. F, 5/13/10
May, 2010
47
ICS1893BF Data Sheet Rev. F - Release
Copyright 2009, IDT, Inc.
All rights reserved.
Note: The Management Frame Structure starts from and returns to an IDLE condition. However, the IDLE
periods are not part of the Management Frame Structure.
6.6.2.1 Management Frame Preamble
The ICS1893BF continually monitors its serial management interface for either valid data or a Management
Frame (MF) Preamble, based upon the setting of the MF Preamble Suppression bit, 1.6. When the MF
Preamble Suppression is disabled, an ICS1893BF waits for a MF Preamble which indicates the start of an
STA transaction. A Management Frame Preamble is a pattern of 32 contiguous logic one bits on the MDIO
pin, along with 32 corresponding clock cycles on the MDC pin.
The ICS1893BF supports the Management Frame (MF) Preamble Suppression capability on its
Management Interface, thereby providing a method to shorten the Management Frame and provide an STA
with faster access to the Management Registers.
The ability to process Management Frames that do not have a preamble is provided by the Management
Frame Preamble Suppression bit, (bit 1.6 in the ICS1893BF’s Status Register). This is an ISO/IEC defined
status bit that is intended to provide an indication of whether or not a PHY supports the MF Preamble
Suppression feature. In order to maintain backward compatibility with the ICS1890, which did not support
MF Preamble Suppression, the ICS1893BF MF Preamble Suppression bit is a Command Override Write
bit which defaults to a logic zero. An STA can enable MF Preamble Suppression by writing a logic one to bit
1.6 subsequent to a write of logic one to the Command Override bit, 16.15. For an explanation of the
Command Override Write bits, see Section 7.1.2, “Management Register Bit Access”.
6.6.2.2 Management Frame Start
A valid Management Frame includes a start-of-frame delimiter, SFD, immediately following the preamble.
The SFD bit pattern is 01b and is synchronous with two clock cycles on the MDC pin.
6.6.2.3 Management Frame Operation Code
A valid Management Frame includes an operation code (OP) immediately following the start-of-frame
delimiter. There are two valid operation codes: one for reading from a management register, 10b, and one
for writing to a management register, 01b. The ICS1893BF does not respond to the codes 00b and 11b,
which the ISO/IEC specification defines as invalid.
6.6.2.4 Management Frame PHY Address
The two-wire, Serial Management Interface is specified to allow busing (that is, the sharing of the two wires
among multiple PHYs). The Management Frame includes a 5-bit PHY Address field, PHYAD, allowing for
32 unique addresses. An STA uniquely identifies each of the PHYs that share a single serial management
interface by using this 5-bit PHY Address field, PHYAD.
Table 6-1. Management Frame Structure Summary
Frame Field
Data
Comment
Acronym
Frame Function
PRE
Preamble (Bit 1.6)
11..11
32 ones
SFD
Start of Frame
01
2 bits
OP
Operation Code
10/01 (read/write)
2 bits
PHYAD
PHY Address (Bits 16.10:6)
AAAAA
5 bits
REGAD
Register Address
RRRRR
5 bits
TA
Turnaround
Z0/10 (read/write)
2 bits
DATA
Data
DDD..DD
16 bits
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| ICS1893BFIT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893BFLF | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893BFLFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893BFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893BK | 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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