參數(shù)資料
型號： ICS1893BFILFT
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 118/133頁
文件大小： 0K
描述： PHYCEIVER LOW PWR 3.3V 48-SSOP
標準包裝： 1,000
系列： PHYceiver™
類型： PHY 收發(fā)器
規(guī)程： MII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 48-SSOP
包裝： 帶卷 (TR)
其它名稱： 1893BFILFT
Chapter 7 Management Register Set
ICS1893BF, Rev. F, 5/13/10
May, 2010
85
ICS1893BF Data Sheet Rev. F - Release
Copyright 2009, IDT, Inc.
All rights reserved.
7.13.2 Polarity Reversed (bit 18.14)
The Polarity Reversed bit is used to inform an STA whether the ICS1893BF has detected that the signals
on the Twisted-Pair Receive Pins (TP_RXP and TP_RXN) are reversed. When the signal polarity is:
Correct, the ICS1893BF sets bit 18.14 to a logic zero.
Reversed, the ICS1893BF sets bit 18.14 to logic one.
Note: The ICS1893BF can detect this situation and perform all its operations normally, independent of
the reversal.
7.13.3 ICS Reserved (bits 18.13:6)
See Section 7.11.2, “ICS Reserved (bits 16.14:11)”, the text for which also applies here.
7.13.4 Jabber Inhibit (bit 18.5)
The Jabber Inhibit bit allows an STA to disable Jabber Detection. When an STA sets this bit to:
Zero, the ICS1893BF enables 10Base-T Jabber checking.
One, the ICS1893BF disables its check for a Jabber condition during data transmission.
7.13.5 ICS Reserved (bit 18.4)
See Section 7.11.2, “ICS Reserved (bits 16.14:11)”, the text for which also applies here.
7.13.6 Auto Polarity Inhibit (bit 18.3)
The Auto Polarity Inhibit bit allows an STA to prevent the automatic correction of a polarity reversal on the
Twisted-Pair Receive pins (TP_RXP and TP_RXN). If an STA sets this bit to logic:
Zero (the default), the ICS1893BF automatically corrects a polarity reversal on the Twisted-Pair Receive
pins.
One, the ICS1893BF either disables or inhibits the automatic correction of reversed Twisted-Pair
Receive pins.
Note: The ICS1893BF will not complete the Auto-MDIX function for an inverted polarity cable. This
is a rare event with modern manufactured cables. Full Auto-Negotiation and Auto Polarity
Correction will complete when the Auto-MDIX function is disabled. Software control for the
Auto-MDIX function is available in MDIO Register 19 Bits 9:8.
7.13.7 SQE Test Inhibit (bit 18.2)
The SQE Test Inhibit bit allows an STA to prevent the generation of the Signal Quality Error pulse. When an
STA sets this bit to logic:
Zero, the ICS1893BF enables its SQE Test generation.
One, the ICS1893BF disables its SQE Test generation.
The SQE Test provides the ability to verify that the Collision Logic is active and functional. A 10Base-T SQE
test is performed by pulsing the Collision signal for a short time after each packet transmission completes,
that is, after TXEN goes inactive.
Note:
1. The SQE Test is automatically inhibited in full-duplex and repeater modes, thereby disabling the
functionality of this bit.
2. This bit is a control bit and not a status bit. Therefore, it is not updated to indicate this automatic
inhibiting of the SQE test in full-duplex mode or repeater mode.
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ICS1893BFLF 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893BFLFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893BFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
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