參數(shù)資料
型號： ICS1893AFLFT
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 8/136頁
文件大?。?/td> 0K
描述： PHYCEIVER LOW PWR 3.3V 48-SSOP
標(biāo)準(zhǔn)包裝： 1,000
系列： PHYceiver™
類型： PHY 收發(fā)器
規(guī)程： MII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 48-SSOP
包裝： 帶卷 (TR)
其它名稱： 1893AFLFT
Chapter 9
Pin Diagram, Listings, and Descriptions
ICS1893AF, Rev. D 10/26/04
October, 2004
105
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
9.2.4
MAC Interface Pins
This section lists pin descriptions for each of the following interfaces
9.2.4.1
MAC Interface Pins for Media Independent Interface
Table 9-8 lists the MAC/Repeater Interface pin descriptions for the MII.
Table 9-8.
MAC/Repeater Interface Pins: Media Independent Interface (MII)
Pin
Name
Pin
Number
Pin
Type
Pin Description
COL
43
Output
Collision (Detect).
The ICS1893AF asserts a signal on the COL pin when the ICS1893AF
detects receive activity while transmitting (that is, while the TXEN signal is
asserted by the MAC/repeater, that is, when transmitting). When the
mode is:
10Base-T, the ICS1893AF detects receive activity by monitoring the
un-squelched MDI receive signal.
100Base-TX, the ICS1893AF detects receive activity when there are
two non-contiguous zeros in any 10-bit symbol derived from the MDI
receive data stream.
Note:
1. The signal on the COL pin is not synchronous to either RXCLK or
TXCLK.
2. In full-duplex mode, the COL signal is disabled and always remains
low.
3. The COL signal is asserted as part of the signal quality error (SQE)
test. This assertion can be suppressed with the SQE Test Inhibit bit (bit
18.2).
CRS
44
Output
Carrier Sense.
When the ICS1893AF mode is:
Half-duplex, the ICS1893AF asserts a signal on its CRS pin when it
detects either receive or transmit activity.
Either full-duplex or Repeater mode, the ICS1893AF asserts a signal
on its CRS pin only in response to receive activity.
Note: The signal on the CRS pin is not synchronous to the signal on
either the RXCLK or TXCLK pin.
MDC
27
Input
Management Data Clock.
The ICS1893AF uses the signal on the MDC pin to synchronize the
transfer of management information between the ICS1893AF and the
Station Management Entity (STA), using the serial MDIO data line. The
MDC signal is sourced by the STA.
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參數(shù)描述
ICS1893AFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
ICS1893AG 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGI 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGILF 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGLF 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
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