參數(shù)資料
型號： ICS1893AFILFT
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 50/136頁
文件大?。?/td> 0K
描述： PHYCEIVER LOW PWR 3.3V 48-SSOP
標準包裝： 1,000
系列： PHYceiver™
類型： PHY 收發(fā)器
規(guī)程： MII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 48-SSOP
包裝： 帶卷 (TR)
其它名稱： 1893AFILFT
ICS1893AF, Rev D 10/26/04
October, 2004
20
Chapter 5
Operating Modes Overview
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
5.1.2
Specific Reset Operations
This section discusses the following specific ways that the ICS1893AF can be reset:
Hardware reset (using the RESETn pin)
Power-on reset (applying power to the ICS1893AF)
Software reset (using Control Register bit 0.15)
Note:
At the completion of a reset (either hardware, power-on, or software), the ICS1893AF sets all
registers to their default values.
5.1.2.1
Hardware Reset
Entering Hardware Reset
Holding the active-low RESETn pin low for a minimum of five REF_IN clock cycles initiates a hardware
reset (that is, the ICS1893AF enters the reset state). During reset, the ICS1893AF executes the steps
Exiting Hardware Reset
After the signal on the RESETn pin transitions from a low to a high state, the ICS1893AF completes in 640
ns (that is, in 16 REF_IN clocks) steps 1 through 5, listed in Section 5.1.1.2, “Exiting Reset”. After the first
five steps are completed, the Serial Management Port is ready for normal operations, but this action does
not signify the end of the reset cycle. The reset cycle completes when the transmit clock (TXCLK) and
receive clock (RXCLK) are available, which is typically 53 ms after the RESETn pin goes high. [For details
Note:
1.
The MAC/Repeater Interface is not available for use until the TXCLK and RXCLK are valid.
2.
The Control Register bit 0.15 does not represent the status of a hardware reset. It is a self-clearing bit
that is used to initiate a software reset.
5.1.2.2
Power-On Reset
Entering Power-On Reset
When power is applied to the ICS1893AF, it waits until the potential between VDD and VSS achieves a
minimum voltage before entering reset and executing the steps listed in Section 5.1.1.1, “Entering Reset”.
After entering reset from a power-on condition, the ICS1893AF remains in reset for approximately 20
s.
(For details on this transition, see Section 10.5.15, “Reset: Power-On Reset”.)
Exiting Power-On Reset
The ICS1893AF automatically exits reset and performs the same steps as for a hardware reset. (See
Note:
The only difference between a hardware reset and a power-on reset is that during a power-on
reset, the ICS1893AF isolates its RESETn input pin. All other functionality is the same. As with a
hardware reset, Control Register bit 0.15 does not represent the status of a power-on reset.
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