參數(shù)資料
型號(hào)： IC42S81600L-6TI(G)
英文描述： 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述： 4（2）M中的x 8（16）位× 4銀行（128 - Mbit的）同步動(dòng)態(tài)RAM
文件頁(yè)數(shù)： 8/69頁(yè)
文件大?。?/td> 1118K
代理商： IC42S81600L-6TI(G)
IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
16
Integrated Circuit Solution Inc.
DR023-0E 6/11/2004
Initiallization
Before starting normal operation, the following power on
sequence is necessary to prevent SDRAM from damged
or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE
high , DQN high and NOP condition at the inputs.
2. Maintain stable power, table clock , and NOP input
conditions for a minimum of 200us.
3. Issue precharge commands for all bank. (PRE or
PALL)
4. After all banks become idle state (after tRP), issue 8 or
more auto-refresh commands.
5. Issue a mode register set command to initialize the
mode regiser.
After these sequence, the SDRAM is in idle state and
ready for normal operation.
Programming the Mode Register
The mode register is programmed by the mode register
set command using address bits A13 through A0 as data
inputs. The register retains data until it is reprogrammed
or the device loses power.
The mode register has four fields;
Options : A13 through A7
CAS latency : A6 through A4
Wrap type : A3
Burst length : A2 through A0
Following mode register programming, no command can
be asserted befor at least two clock cycles have elapsed.
CAS
CAS Latency
CAS latency is the most critical parameter being set. It
tells the device how many clocks must elapse before the
data will be available.
The value is determined by the frequency of the clock and
the speed grade of the device. The value can be pro-
grammed as 2 or 3.
Burst Length
Burst Length is the number of words that will be output or
input in read or write cycle. After a read burst is completed,
the output bus will become high impedance.
The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data
will be addressed. The order is programmable as either
“Sequential” or “Interleave”. The method chosen will
depend on the type of CPU in the system.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IC42S81600L-7T 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM
IC42S81600L-7T(G) 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM
IC42S81600L-7TG 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM
IC42S81600L-7TI 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM
IC42S81600L-7TI(G) 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM
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