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參數(shù)資料
| 型號(hào)： | IC42S81600L-6TI(G) |
| 英文描述： | 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 4（2）M中的x 8（16）位× 4銀行（128 - Mbit的）同步動(dòng)態(tài)RAM |
| 文件頁(yè)數(shù)： | 21/69頁(yè) |
| 文件大小： | 1118K |
| 代理商： | IC42S81600L-6TI(G) |
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IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
28
Integrated Circuit Solution Inc.
DR023-0E 6/11/2004
Precharge Termination in WRITE Cycle
During WRITE cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command. The DQM must be high to mask
invalid data in.
During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However, invalid
data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be
high at the same clock as the precharge command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
Burst lengh = X
CLK
Command
CAS latency = 2
DQM
Hi - Z
Write
T0
T1
T2
T3
T4
T5
T6
T7
T8
tRP
PRE
ACT
DQ
Write
PRE
ACT
tRP
CAS latency = 3
Hi - Z
D0
D3
D2
D1
D0
D3
D2
D1
DQM
D4
command
DQ
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC42S81600L-7T | 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-7T(G) | 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-7TG | 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-7TI | 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-7TI(G) | 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
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