參數(shù)資料
型號: IC42S16400A-7BIG
英文描述: 1M x 16Bit x 4 Banks (64-MBIT) SDRAM
中文描述: 100萬× 16 × 4銀行(64兆位)內(nèi)存
文件頁數(shù): 22/67頁
文件大?。?/td> 1072K
代理商: IC42S16400A-7BIG
IC42S16400A
22
Integrated Circuit Solution Inc.
DR039-0A 02/19/2004
Read / Write Command Interval
Read to Read Command Interval
During a read cycle when a new read command is asserted, it will be effective after the
CAS
latency, even if the previous
read operation has not completed. READ will be interrupted by another READ.
Each read command can be asserted in every clock without any restriction.
Write to Write Command Interval
During a write cycle, when a new Write command is asserted, the previous burst will terminate and the new burst will begin
with a new write command. WRITE will be interrupted by another WRITE.
Each write command can be asserted in every clock without any restriction.
READ to READ Command Interval
Burst lengh=4, CAS latency=2
CLK
Command
DQ
QA0
QB2
QB1
QB0
Read A
T0
T1
T2
T3
T4
T5
T6
T7
Hi-Z_
T8
1 cycle
QB3
Read B
Burst lengh=4, CAS latency=2
CLK
Command
DQ
QA0
QB2
QB1
QB0
Write A
T0
T1
T2
T3
T4
T5
T6
T7
Hi-Z_
T8
1 cycle
QB3
Write B
WRITE to WRITE Command Interval
相關(guān)PDF資料
PDF描述
IC42S16400A-7T 1M x 16Bit x 4 Banks (64-MBIT) SDRAM
IC42S16400A-7TG 1M x 16Bit x 4 Banks (64-MBIT) SDRAM
IC42S16400A-7TI 1M x 16Bit x 4 Banks (64-MBIT) SDRAM
IC42S16400A-7TIG 1M x 16Bit x 4 Banks (64-MBIT) SDRAM
IC42S16800-8TI 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IC42S16400A-7T 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16Bit x 4 Banks (64-MBIT) SDRAM
IC42S16400A-7TG 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16Bit x 4 Banks (64-MBIT) SDRAM
IC42S16400A-7TI 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16Bit x 4 Banks (64-MBIT) SDRAM
IC42S16400A-7TIG 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16Bit x 4 Banks (64-MBIT) SDRAM
IC42S16400F-5TL 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM