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參數(shù)資料
| 型號： | IC42S16100-7TIG |
| 英文描述： | 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 為512k × 16位× 2組（16兆）同步動態(tài)RAM |
| 文件頁數(shù)： | 31/78頁 |
| 文件大小： | 789K |
| 代理商： | IC42S16100-7TIG |
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IC42S16100
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
31
CAS
latency = 2, 3, burst length = 4
Write Cycle Interruption Using the
Precharge Command
A write cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (t
WDL
) from the precharge command to the point
where burst input is invalid, i.e., the point where input data
is no longer written to device internal memory is zero clock
cycles regardless of the
CAS
.
To inhibit invalid write, the DQM signal must be asserted
HIGH with the precharge command.
This precharge command and burst write command must
be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of dual bank operation.
PRE 0
WRITE A0
COMMAND
DQM
I/O
CLK
D
IN
A0
D
IN
A1
D
IN
A2
D
IN
A3
t
WDL
=0
WRITE (CA=A, BANK 0)
PRECHARGE (BANK 0)
MASKED BY DQM
PRE 0
WRITE A0
COMMAND
I/O
CLK
D
IN
A0
D
IN
A1
D
IN
A2
D
IN
A3
t
DPL
WRITE (CA=A, BANK 0)
PRECHARGE (BANK 0)
CAS
Latency
t
WDL
3
0
2
0
t
DPL
1
1
Inversely, to write all the burst data to the device, the
precharge command must be executed after the write data
recovery period (t
DPL
) has elapsed. Therefore, the
precharge command must be executed on one clock cycle
that follows the input of the last burst data item.
CAS
latency = 2, 3, burst length = 4
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相關代理商/技術參數(shù) |
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|---|---|
| IC42S16101 | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
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| IC42S16101-5BIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16101-5T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16101-5TG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
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