參數(shù)資料
型號(hào)： IBMPPC750CLGEQ6024
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 600 MHz, RISC PROCESSOR, PBGA278
封裝： 21 X 21 MM, 1 MM PITCH, PLASTIC, MS-034, FCBGA-278
文件頁數(shù)： 7/65頁
文件大?。?/td> 930K
代理商： IBMPPC750CLGEQ6024
Datasheet
DD2.x
Preliminary
PowerPC 750CL Microprocessor
750cl_ds_body.fm.2.4
May 29, 2007
Electrical and Thermal Characteristics
Page 15 of 65
3. Electrical and Thermal Characteristics
This section provides AC and DC electrical specifications and thermal characteristics for the 750CL.
3.1 DC Electrical Characteristics
The tables in this section describe the DC electrical characteristics for the 750CL.
Table 3-1. Absolute Maximum Ratings
Characteristic
Symbol
1.15 V
1.8 V
Units
Notes
Core supply voltage
VDD
-0.3 to 1.4
V
3, 4
Phase-locked loop (PLL) supply voltage
AVDD
-0.3 to 1.4
V
60x bus supply voltage
OVDD
-0.3 to 1.4
-0.3 to 2.0
V
3, 4
Input voltage
VIN
-0.3 to 1.4
-0.3 to 2.0
V
Storage temperature range
TSTG
JEDEC J-STD-033
°C
Notes:
1. Functional and tested operating conditions are given in Table 3-2 Recommended Operating Conditions. Absolute maximum ratings
are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed above may
affect device reliability or cause permanent damage to the device.
2. Caution: Transient VIN overshoots of up to OVDD + 0.8 V, with a maximum of 2.6 V for 1.8 V operation, and undershoots down to
GND – 0.8 V, are allowed for up to 5 ns.
3. Caution: OVDD must not exceed VDD/AVDD by more than 1.8 V continuously. OVDD may exceed VDD/AVDD by up to 2.0 V for up
to 20 ms during power-on or power-off. OVDD must not exceed VDD/AVDD by more than 2.0 V for any amount of time.
4. Caution: VDD/AVDD must not exceed OVDD by more than 1.0 V continuously. VDD/AVDD may exceed OVDD by up to 1.4 V for up
to 20 ms during power-on or power-off. VDD/AVDD must not exceed OVDD by more than 1.4 V for any amount of time.
5. Caution: AVDD must not exceed VDD by more than 0.5 V at any time.
6. Electrostatic discharge (ESD) ratings:
M
=
200 V
EIA/JEDEC Standard JESD22-A115-A
CDM =
800 V
JEDEC TM C101B.01
HBM = 1000 V
EIA/JEDEC Standard JESD22-A114-C
Table 3-2. Recommended Operating Conditions
Characteristic
Symbol
Value
Unit
Notes
Core supply voltage
VDD
See note 2
V
60X bus I/O supply voltage (1.15 V)
OVDD
1.15±.05
V
60X bus I/O supply voltage (1.8 V)
OVDD
1.8±5%
V
PLL supply voltage
AVDD
See note 2
V
Input voltage
VIN
GND to OVDD
V
Die-junction temperature
TJ
0 to 105
°C
Notes:
1. See Section 5.3, PLL Power Supply Filtering, on page 39 for AVDD noise filtering requirements.
2. The core supply voltage (VDD) and PLL supply voltage (AVDD) are specified by the part number. See Section 1.3, Part Number
Information, on page 12 for the recommended operating VDD range for each part number.
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