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參數(shù)資料
| 型號(hào)： | IBMPPC750CLGEQ6024 |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 600 MHz, RISC PROCESSOR, PBGA278 |
| 封裝： | 21 X 21 MM, 1 MM PITCH, PLASTIC, MS-034, FCBGA-278 |
| 文件頁(yè)數(shù)： | 2/65頁(yè) |
| 文件大?。?/td> | 930K |
| 代理商： | IBMPPC750CLGEQ6024 |
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Datasheet
DD2.x
PowerPC 750CL Microprocessor
Preliminary
General Information
Page 10 of 65
750cl_ds_body.fm.2.4
May 29, 2007
Fixed-point units
Fixed-Point Unit 1 (FXU1): multiply, divide, shift, rotate, arithmetic, logical
Fixed-Point Unit 2 (FXU2): shift, rotate, arithmetic, logical
Single-cycle arithmetic, shift, rotate, logical
Multiply and divide support (multi-cycle)
Early out multiply
Floating-point unit
Support for IEEE-754 standard single-precision and double-precision floating-point arithmetic
3-cycle latency, 1-cycle throughput, single-precision multiply-add
3-cycle latency, 1-cycle throughput, double-precision add
4-cycle latency, 2-cycle throughput, double-precision multiply-add
Hardware support for divide
Hardware support for denormalized numbers
Time deterministic non-IEEE mode
System unit
Executes CR logical instructions and miscellaneous system instructions
Has special register transfer instructions
Level 1 (L1) cache structure
32K, 32-byte line, 8-way set associative instruction cache
32K, 32-byte line, 8-way set associative data cache
Single-cycle cache access
Pseudo least-recently-used (PLRU) replacement
Copy-back or write-through data cache (on a page per page basis)
Supports PowerPC memory coherency modes
Nonblocking instruction and data cache (supports hits under one outstanding miss)
No snooping of instruction cache
Memory management unit
128 entry, 2-way set associative instruction TLB
128 entry, 2-way set associative data TLB
Hardware reload for TLBs
Eight instruction block address translation (BAT) arrays and eight data BATs
Virtual memory support for up to 4 petabytes (252) virtual memory
Real memory support for up to 4 gigabytes (232) of physical memory
Level 2 (L2) cache
256 KB, 64-byte line, 2-way set associative on-chip cache memory
Internal L2 cache controller with 2K-entry tag array
Copy-back or write-through data cache (on a page basis, or for all L2)
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