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參數(shù)資料
| 型號： | IBM43GAENGP0002 |
| 廠商： | IBM Microeletronics |
| 英文描述： | IBM Global Positioning Satellite Receiver(IBM全球定位衛(wèi)星接收器) |
| 中文描述： | IBM全球定位衛(wèi)星接收機（IBM的全球定位衛(wèi)星接收器） |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 155K |
| 代理商： | IBM43GAENGP0002 |
IBM43GAENGP0002
IBM Global Positioning Satellite Receiver
General Information
Page 2 of 11
GP0001ds.fm (02)
August 11, 2000
1.3 Ordering Information
1.4 Receiver Architecture
The functional architecture of the IBM GPS Receiver is shown in the block diagram below. The IBM GPS
Receiver chip set includes all the radio frequency (RF) direct sampling and amplification circuitry. These
circuits present both the sign (
±)
and magnitude of sampled data to the Digital ASIC. The Digital ASIC
contains an integral microprocessor (401 PowerPC
) and all GPS signal processing hardware. Memory and
other supporting components are needed to make a complete navigation system.
1.5 Receiver Operation
The receiver requires 3.3 V DC primary input power.
The receiver
’
s antenna must have visibility of the sky in order to acquire enough satellites to produce a navi-
gation solution. While this is usually not a problem outdoors, operation indoors or in a vehicle may require that
the antenna be located with an unobstructed view of the sky. If the satellites are blocked from the receiver
’
s
antenna, the receiver will take longer to acquire a position. If fewer than three satellites are available, the
receiver may not be able to determine a valid position solution.
Part Number
Product Name
IBM43GAENGP0002
IBM Global Positioning Satellite Receiver
Figure 1: GPS Engine Block Diagram
RF Shield
DCAM
Input/Output
Connector
Flash
Memory
RAM
RTC
Crystal
Real
Time
Clock
Temperature
Digital
ASIC
RF
ASIC
Reference
Crystal
Low
Noise
Amplifier
(LNA)
RF
Filter
RF
Connector
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