參數(shù)資料
型號： IBM25PPC750GXECR5H83T
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 933 MHz, RISC PROCESSOR, CBGA292
封裝： 21 X 21 MM, 1 MM PITCH, LEAD FREE, CERAMIC, BGA-292
文件頁數(shù)： 68/74頁
文件大?。?/td> 1054K
代理商： IBM25PPC750GXECR5H83T
Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
System Design Information
Page 70 of 73
750GX_ds_body.fm SA14-2765-02
September 2, 2005
5.9.3 I/O Voltage Mode Selection
Selection between 1.8 V, 2.5 V, or 3.3 V I/O modes is accomplished by using the BVSEL and L1_TSTCLK
pins:
If BVSEL = 1 and L1_TSTCLK = 0, then the 3.3 V mode is enabled.
If BVSEL = 1 and L1_TSTCLK = 1, then the 2.5 V mode is enabled.
If BVSEL = 0 and L1_TSTCLK = 1, then the 1.8 V mode is enabled.
Note: Do not set BVSEL = 0 and L1_TSTCLK = 0 since it yields an invalid mode.
5.9.4 QACK Signal Implementation for Selected Features
5.9.4.1 Precharge Duration Selection and Application
An extended precharge feature is available for the signals ABB, DBB, and ARTRY in situations where the
loading and net topology of these signals requires a longer precharge duration for the signals to attain a valid
level.
This feature has not been fully tested and should not be necessary in a properly designed system, even at
200 MHz. System designers should assume standard precharge as the default selection, with an option to
use extended precharge.
The bus signals, ABB, DBB, and ARTRY, require a precharge to the inactive state (bus high) before going to
tristate. The precharge duration in standard precharge mode is approximately one half cycle, and should be
used for systems with point-to-point topologies. Extended precharge mode increases the precharge duration
to one cycle. This increase may be required for bus speeds approaching 200 MHz when bus loading is high.
QACK in a logical high state at the transition of HRESET from asserted to negated enables standard pre-
charge mode in the 750GX. QACK in a logical low state at the transition of HRESET from asserted to negated
enables extended pre-charge mode in the 750GX.
Table 5-10. Summary of Mode Select
Mode
750GX
32-bit mode
Sample TLBISYNC to select
High = 64-bit mode
Low = 32-bit mode
Data retry mode
Selects DRTRY mode.
0 at HRESET transition
No DRTRY mode
1 at HRESET transition
DRTRY mode
Factory usage modes
Factory usage modes are selected by sensing the data bus disable (DBDIS),
data bus write-only (DBWO), and L2_TSTCLK pins at the transition of
HRESET from low to high. These pins should be held inactive (high) at the
HRESET transition for normal machine operation.
I/O mode selection
3.3 V
±165 mV (BVSEL = 1, L1_TSTCLK = 0) or
2.5 V
±125 mV (BVSEL = 1, L1_TSTCLK = 1) or
1.8 V
±100 mV (BVSEL = 0, L1_TSTCLK = 1)
Standard/extended precharge mode
QACK in a logical high state at the transition of HRESET from asserted to
negated enables standard precharge mode, the recommended default. See
Section 5.9.4.1 for details.
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