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參數(shù)資料
| 型號： | IBM25PPC750GXECR5H83T |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 933 MHz, RISC PROCESSOR, CBGA292 |
| 封裝： | 21 X 21 MM, 1 MM PITCH, LEAD FREE, CERAMIC, BGA-292 |
| 文件頁數(shù)： | 49/74頁 |
| 文件大?。?/td> | 1054K |
| 代理商： | IBM25PPC750GXECR5H83T |
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Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
750GX_ds_body.fm SA14-2765-02
September 2, 2005
System Design Information
Page 53 of 73
High-frequency decoupling capacitors should be located as close as possible to the processor with low lead
inductance to the ground and voltage planes.
Decoupling capacitors are recommended on the back of the card, directly opposite the module. The recom-
mended placement and number of decoupling capacitors, 34 VDD-GND capacitors and 44 OVDD-GND
capacitors, are described in Figure 5-4 on page 54. The recommended decoupling capacitor specifications
are provided in Table 5-4. The placement and usage described here are guidelines for decoupling capacitors
and should be applied for system designs.
Note: The decoupling capacitor electrodes are located directly opposite their corresponding BGA pins where
possible. Also, each electrode for each decoupling capacitor needs to be connected to one or more BGA pins
(balls) with a short electrical path. Thus, through-vias adjacent to the decoupling capacitors are recom-
mended.
The card designer can expand on the decoupling capacitor recommendations by doing the following:
Adding additional decoupling capacitors.
If using additional decoupling capacitors, verify that these additional capacitors do not reduce the number
of card vias or cause the vias to lose proximity to each capacitor electrode.
Adding additional through-vias or blind-vias.
Card technologies are available that will reduce the inductance between the decoupling capacitor and the
BGA pin (ball). Replacing single vias with multiple vias is certainly approved. Place GND vias close to
VDD or OVDD vias to reduce loop inductance.
Figure 5-4 on page 54 shows the mapping of Power, Ground, and Signal pin assignments, and recom-
mended layout of decoupling capacitors under application conditions. In test mode, pins C11 and G8 can be
used as Kelvin probes, in which case the pins should be disconnected from card GND and VDD. Capacitors
should not be connected to the Kelvin pins during Kelvin probe voltage measurements.
Table 5-4. Recommended Decoupling Capacitor Specifications
Item
Description
Decoupling capacitor specifications:
Type X5R or Y5V
10 V minimum
0402 size
40 × 20 mils, nominally
1.0 mm × 0.5 mm
±0.1 mm on both dimensions
100 nF
Recommended minimum number of decou-
pling capacitors on the back of the card:
34 VDD-GND capacitors
44 OVDD-GND capacitors
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IBM25PPC750GXECR6542T | 制造商:IBM 功能描述:POLARIS 1.2 ? 21CBGA293 GR2 LIDLESS 1G - Trays |
| IBM25PPC750GXECR6542V | 制造商:IBM 功能描述:POLARIS 1.2 ? 21CBGA293 GR2 LIDLESS 1G - Trays |
| IBM25PPC750GXECR6582T | 制造商:IBM 功能描述:POLARIS 1.2 ? 21CBGA293 GR2 LIDLS ? 1GHZ - Trays 制造商:IBM 功能描述:IBMIBM25PPC750GXECR6582T MPU 21CBGA293 |
| IBM25PPC750GXECR6582V | 制造商:IBM 功能描述:POLARIS 1.2 ? 21CBGA293 GR2 LIDLS ? 1GHZ - Trays |
| IBM25PPC750GXECR6H42T | 制造商:IBM 功能描述:POLARIS 1.2 ? 21CBGA293 GR2 LIDLS 1GHZ - Trays |
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