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參數(shù)資料
| 型號： | IBM25PPC750CXEJQ7023T |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 600 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | 27 X 27 MM, LEAD FREE, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 44/44頁 |
| 文件大?。?/td> | 416K |
| 代理商： | IBM25PPC750CXEJQ7023T |
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Data Sheet
Preliminary
PowerPC 750CXe RISC Microprocessor
750cxe_DD3.1_Dev_3_gen_mkt.fm.1.5
April 8, 2004
General Information
Page 1 of 36
1. General Information
The PowerPC 750CXe RISC Microprocessor is an
implementation of the PowerPC family of reduced
instruction set computer (RISC) microprocessors.
The information in this document is specific to
revision DD 3.1 of the 750CEx and may not apply
to subsequent revisions.
1.1 Features
This section summarizes the major features of the
PowerPC 750CXe implementation of the PowerPC
architecture.
Branch processing unit
- Four instructions fetched per clock
- One branch processed per cycle (plus
resolving 2 speculations)
- Up to 1 speculative stream in execution, 1
additional speculative stream in fetch
- 512-entry branch history table (BHT) for
dynamic prediction
- 64-entry, 4-way set associative branch
target instruction cache (BTIC) for
eliminating branch delay slots
Dispatch unit
- Full hardware detection of dependencies
(resolved in the execution units)
- Dispatch two instructions to six independent
units (system, branch, load/store, fixed-
point unit 1, fixed-point unit 2, or floating-
point)
- 4-stage pipeline: fetch, dispatch, execute,
and complete
- Serialization control (predispatch,
postdispatch, execution, serialization)
Fixed-point units
- Fixed-point unit 1 (FXU1); multiply, divide,
shift, rotate, arithmetic, logical
- Fixed-point unit 2 (FXU2); shift, rotate,
arithmetic, logical
- Single-cycle arithmetic, shift, rotate, logical
- Multiply and divide support (multi-cycle)
- Early out multiply
- Thirty-two, 32-bit general purpose registers
- Secondary FXU executes integer
add/compare instructions
Decode
- Register file access
- Forwarding control
- Partial instruction decode
Load/store unit
- One cycle load or store cache access (byte,
half-word, word, double-word)
- Effective address generation
- Hits under misses (one outstanding miss)
- Single-cycle misaligned access within
double word boundary
- Alignment, zero padding, sign extend for
integer register file
- Floating-point internal format conversion
(alignment, normalization)
- Sequencing for load/store multiples and
string operations
- Store gathering
- Cache and TLB instructions
- Big and little-endian byte addressing
supported
- Misaligned little-endian support in hardware
Floating-point unit
- Support for IEEE-754 standard single and
double-precision floating-point arithmetic
- Optimized for single-precision multiply/add
- Thirty-two, 64-bit floating point registers
- Enhanced reciprocal estimates
- 3-cycle latency, 1-cycle throughput, single-
precision multiply-add
- 3-cycle latency, 1-cycle throughput, double-
precision add
- 4-cycle latency, 2-cycle throughput, double-
precision multiply-add
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IBM25PPC750FL-GR0123V | 制造商:IBM 功能描述:MPU 750XX RISC 32BIT - Trays |
| IBM25PPC750FL-GR0124V | 制造商:IBM 功能描述:MPU 750XX RISC 32BIT - Trays |
| IBM25PPC750FL-GR0133T | 制造商:IBM 功能描述:IBMIBM25PPC750FL-GR0133T CSOI9SG LOGIC P |
| IBM25PPC750FL-GR0133V | 制造商:IBM 功能描述:MPU 750XX RISC 32BIT - Trays |
| IBM25PPC750FL-GR1024T | 制造商:IBM 功能描述: |
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