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| 型號(hào)： | IBM25PPC405GP-3EE266C |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266.66 MHz, RISC PROCESSOR, PBGA413 |
| 封裝： | 25 X 25 MM, ENHANCED, PLASTIC, BGA-413 |
| 文件頁數(shù)： | 53/60頁 |
| 文件大?。?/td> | 1480K |
| 代理商： | IBM25PPC405GP-3EE266C |
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PowerPC 405GP Embedded Processor Data Sheet
6/20/03
Page 57 of 60
PCI Divider from PLB 2, 3
D18/A20
GPIO1[TS1E]
C20/C19
GPIO2[TS2E]
Divide by 1
0
Divide by 2
0
1
Divide by 3
1
0
Divide by 4
1
External Bus Divider from PLB 2
K25/K20
EMCTxErr
K23/J21
EMCTxEn
Divide by 2
0
Divide by 3
0
1
Divide by 4
1
0
Divide by 5
1
ROM Width
AC2/N3
UART1_Tx
AD2/N7
UART1_RTS/
UART1_DTR
8-bit ROM
0
16-bit ROM
0
1
32-bit ROM
1
0
Reserved
1
ROM Location
U2/P4
HoldAck
PPC405GP Peripheral Attach
0
PPC405GP PCI Attach
1
PCI Asynchronous Mode Enable
Y3/U4
ExtAck
Synchronous PCI Mode
0
Asynchronous Mode
1
PCI Arbiter Enable 3
AF18/AB18
GPIO4[TS2O]
Internal Arbiter Disabled
0
Internal Arbiter Enabled
1
Note:
1. The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the
PPC405GP. These bits are shown for information only; and do not require modification except in special clocking circumstances
such as spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405GP,
visit the technical documents area of the IBM PowerPC web site.
2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in “Clocking
Specifications” on page 47. Further requirements are detailed in the Clocking chapter of the
PowerPC 405GP Embedded
Processor User’s Manual.
3. Additional consideration must be given to pins that normally function as Trace signals. Improved design margin can be gained by
using three-state buffers instead of strapping resistors, and minimizing trace lengths and stubs.
PPC405GP Strapping Pin Assignments (Part 2 of 2)
Function
Option
Ball Strapping
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