參數(shù)資料
型號: IBM25PPC405EP-3GB133CZ
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA385
封裝: 31 MM, ENHANCED, PLASTIC, BGA-385
文件頁數(shù): 44/52頁
文件大?。?/td> 992K
代理商: IBM25PPC405EP-3GB133CZ
Preliminary
PowerPC 405EP Embedded Processor Data Sheet
6/9/03
Page 49 of 52
I/O Specifications—Group 2
Notes:
1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM.
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
3. SDRAM interface hold times are guaranteed at the PPC405EP package pin. System designers must use the
PPC405EP IBIS model (available from www.chips.ibm.com) to ensure their clock distribution topology minimizes
loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal
wiring.
4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
5. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
SDRAM Interface
BA1:0
na
4.7
2
15.3
10.2
MemClkOut
1, 2
BankSel3:0
na
4.5
1.7
15.3
10.2
MemClkOut
1, 2
CAS
na
4.8
2
15.3
10.2
MemClkOut
1, 2
ClkEn0:1
na
4.1
1.6
28.7
19.3
MemClkOut
1, 2
DQM0:3
na
4.7
1.9
15.3
10.2
MemClkOut
1, 2
MemAddr12:00
na
4.8
2.1
15.3
10.2
MemClkOut
1, 2
MemData00:31
1.6
1
4
1.2
15.3
10.2
MemClkOut
1, 2
RAS
na
5
2.1
15.3
10.2
MemClkOut
1, 2
WE
na
4.9
2
15.3
10.2
MemClkOut
1, 2
External Slave Peripheral Interface
PerAddr06:31
na
3.8
1.6
15.3
10.2
PerClk
[PerBLast]
4
1
8
0128
PerClk
PerCS0
[PerCS1:4]
na
4.1
1.5
10.3
7.1
PerClk
PerData00:31
5
1
6.4
1.5
15.3
10.2
PerClk
PerOE
na
4.1
1.5
10.3
7.1
PerClk
PerR/W
na
4.1
1.6
10.3
7.1
PerClk
PerReady
6.5
1
na
PerClk
PerWBE0:3
na
4.1
1.6
10.3
7.1
PerClk
ExtReset
na
15.3
10.2
PerClk
na
0.4
-0.2
15.3
10.2
PLB Clk
4
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