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參數(shù)資料
| 型號： | IBM25PPC405EP-3GB133CZ |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA385 |
| 封裝： | 31 MM, ENHANCED, PLASTIC, BGA-385 |
| 文件頁數(shù)： | 31/52頁 |
| 文件大?。?/td> | 992K |
| 代理商： | IBM25PPC405EP-3GB133CZ |
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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
6/9/03
Page 37 of 52
JTAG Interface
TDI
Test data in.
I
5V tolerant
3.3V LVTTL
1, 4
TMS
JTAG test mode select.
I
5V tolerant
3.3V LVTTL
1, 4
TDO
Test data out.
O
5V tolerant
3.3V LVTTL
TCK
JTAG test clock. The frequency of this input can range from DC to
25MHz.
I
5V tolerant
3.3V LVTTL
1, 4
TRST
JTAG reset. TRST must be low at power-on to initialize the JTAG
controller and for normal operation of the PPC405EP.
I
5V tolerant
3.3V LVTTL
5
System Interface
SysReset
Main system reset. External logic can drive this bidirectional pin
low (minimum of 16 cycles) to initiate a system reset. A system
reset can also be initiated by software. Implemented as an open-
drain output (two states; 0 or open circuit).
I/O
5V tolerant
3.3V LVTTL
1, 2
SysErr
Set to 1 when a Machine Check is generated.
O
5V tolerant
3.3V LVTTL
6
Halt
Halt from external debugger.
I
5V tolerant
3.3V LVTTL
1, 2
GPIO00:31
General Purpose I/O. All of the GPIO signals are multiplexed with
other signals.
I/O
5V tolerant
3.3V LVTTL
1
TestEn
Test Enable. Used only for manufacturing tests. Pull down for
normal operation.
I
1.8V CMOS
w/pull-down
SysClk
Main system clock input.
I
3.3V LVTTL
[RejectPkt0:1]
External request to reject a packet.
I
5V tolerant
3.3V LVTTL
AVDD
Clean voltage input for the PLL.
I
AGND
Clean Ground input for the PLL.
I
Signal Functional Description (Part 5 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 31 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 31 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 32.
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM25PPC405EP-3GB133C | 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA385 |
| IBM25PPC405GP-3DD200C | RISC PROCESSOR, PBGA456 |
| IBM25PPC405GP-3BD266C | RISC PROCESSOR, PBGA456 |
| IBM25PPC405GP3EE200CZ | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA413 |
| IBM25PPC405GP-3BE200C | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA456 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM25PPC405GP3BC200C | 制造商:IBM 功能描述: |
| IBM25PPC405GP-3BC200C | 制造商:IBM 功能描述: 制造商:IBM 功能描述:Electronic Component |
| IBM25PPC405GP-3BD200C | 制造商:IBM 功能描述: |
| IBM25PPC405GP-3BE200C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|456PIN|PLASTIC |
| IBM25PPC405GP3BE200CZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|456PIN|PLASTIC |
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