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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
6/9/03
Page 31 of 52
Signal List
The following table provides a summary of the number of package pins associated with each functional
interface group.
description of the signal function. Active-low signals (for example, RAS) are marked with an overline. Please
Multiplexed Pins
Some signals are multiplexed on the same package pin (ball) so that the pin can be used for different
functions. In most cases, the signal names shown in this table are not accompanied by signal names that
may be multiplexed on the same pin. If you need to know what, if any, signals are multiplexed with a particular
application a particular pin will always be programmed to serve the same function. The flexibility of
multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible.
In addition to multiplexing, many pins are also multi-purpose. For example, in the PCI interface
PCIC3:0/BE3:0 serves as both Command and Byte Enable signals. In this example, the pins are also
bidirectional, serving as both inputs and outputs.
Initialization Strapping
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs
Note that the use of these pins for strapping is not considered multiplexing since the strapping function is not
programmable.
Pull-Up and Pull-Down Resistors
Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in
an appropriate state. The recommended pull-up value of 3k
to +3.3V (10k to +5V can be used on 5V
tolerant I/Os) and pull-down value of 1k
to GND, applies only to individually terminated signals. To prevent
possible damage to the device, I/Os capable of becoming outputs
must never be tied together and terminated
through a common resistor.
Pin Summary
Group
No. of Pins
Non multiplexed
215
Multiplexed
33
Total Signal Pins
248
OVDD
43
VDD
16
Gnd
53
Thermal (and Gnd)
25
Reserved
0
Total Pins
385