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參數(shù)資料
| 型號： | IBM25PPC405EP-3GB133C |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA385 |
| 封裝： | 31 MM, ENHANCED, PLASTIC, BGA-385 |
| 文件頁數(shù)： | 37/52頁 |
| 文件大小： | 992K |
| 代理商： | IBM25PPC405EP-3GB133C |
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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Page 42 of 52
6/9/03
Test Conditions
Clock timing and switching characteristics are specified in
accordance with operating conditions shown in the table
“Recommended DC Operating Conditions.” For all signals other than
PCI signals, AC specifications are characterized at OVDD = 3V and
TC = 85°C with the 50pF test load shown in the figure at right.
For PCI signals there are two different test load circuits, one for the
rising edge and one the falling edge as shown in the figures at right.
DC Electrical Characteristics
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Active Operating Current (VDD)IDD
440
520
606
mA
Active Operating Current (OVDD)IODD
59
70
81
mA
Active Operating Current (AVDD)IADD
14
17
19
mA
Total Power
PT
1.2
1.4
W
Note:
1. AVDD should be derived from VDD using the following circuit:
VDD
C1
C2
C3
AVDD
L1
L1 – 2.2
H SMT inductor (equivalent to MuRata
LQH3C2R2M34) or SMT chip ferrite bead (equivalent
to MuRata BLM31A700S)
C1 – 3.3
F SMT tantalum
C2 – 0.1
F SMT monolithic ceramic capacitor with X7R
dielectric or equivalent
C3 – 0.01
F SMT monolithic ceramic capacitor with X7R
dielectric or equivalent
+
AGND
GND
Output
Pin
50pF
All signals other
than PCI
Output
Pin
10pF
25
Output
Pin
10pF
25
OVDD
PCI Rising edge
PCI Falling edge
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