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參數(shù)資料
| 型號： | IBM25PPC405EP-3GB133C |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA385 |
| 封裝： | 31 MM, ENHANCED, PLASTIC, BGA-385 |
| 文件頁數(shù)： | 30/52頁 |
| 文件大?。?/td> | 992K |
| 代理商： | IBM25PPC405EP-3GB133C |
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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Page 36 of 52
6/9/03
PerOE
Peripheral output enable.
O
5V tolerant
3.3V LVTTL
7
PerR/W
Peripheral read/write. High indicates a read from memory, low
indicates a write to memory.
O
5V tolerant
3.3V LVTTL
PerReady
Ready to transfer data.
I
5V tolerant
3.3V LVTTL
1
[PerBLast]
Used to indicates the last transfer of a memory access.
To access this function, software must toggle a DCR bit.
I/O
5V tolerant
3.3V LVTTL
1, 7
PerClk
Peripheral clock to be used by peripheral slaves.
O
5V tolerant
3.3V LVTTL
ExtReset
Peripheral reset to be used by peripheral slaves.
O
5V tolerant
3.3V LVTTL
Internal Peripheral Interface
UART0_Rx
UART0 Serial Data In.
I
5V tolerant
3.3V LVTTL
1
UART0_Tx
UART0 Serial Data Out.
O
5V tolerant
3.3V LVTTL
6
[UART0_DCD]
UART0 Data Carrier Detect.
To access this function, software must toggle a DCR bit.
I
5V tolerant
3.3V LVTTL
1
[UART0_DSR]
UART0 Data Set Ready.
To access this function, software must toggle a DCR bit.
I
5V tolerant
3.3V LVTTL
1
UART0_CTS
UART0 Clear To Send.
I
5V tolerant
3.3V LVTTL
1
[UART0_DTR]
UART0 Data Terminal Ready.
To access this function, software must toggle a DCR bit.
O
5V tolerant
3.3V LVTTL
UART0_RTS
UART0 Request To Send.
O
5V tolerant
3.3V LVTTL
6
[UART0_RI]
UART0 Ring Indicator.
To access this function, software must toggle a DCR bit.
I
5V tolerant
3.3V LVTTL
1
[UART1_Rx]
UART1 Serial Data In.
To access this function, software must toggle a DCR bit.
I
5V tolerant
3.3V LVTTL
1
[UART1_Tx]
UART1 Serial Data Out.
To access this function, software must toggle a DCR bit.
O
5V tolerant
3.3V LVTTL
IICSCL
IIC Serial Clock.
I/O
3.3V IIC
1, 2
IICSDA
IIC Serial Data.
I/O
3.3V IIC
1, 2
Interrupts Interface
[IRQ0:6]
Interrupt requests
To access this function, software must toggle a DCR bit.
I
5V tolerant
3.3V LVTTL
1
Signal Functional Description (Part 4 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 31 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 31 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 32.
Signal Name
Description
I/O
Type
Notes
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| IBM25PPC405GP3BC200C | 制造商:IBM 功能描述: |
| IBM25PPC405GP-3BC200C | 制造商:IBM 功能描述: 制造商:IBM 功能描述:Electronic Component |
| IBM25PPC405GP-3BD200C | 制造商:IBM 功能描述: |
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| IBM25PPC405GP3BE200CZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|456PIN|PLASTIC |
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