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參數(shù)資料
| 型號： | IBM25NPE405L-3DA200CZ |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA324 |
| 封裝： | 23 MM, PLASTIC, EBGA-324 |
| 文件頁數(shù)： | 37/48頁 |
| 文件大?。?/td> | 741K |
| 代理商： | IBM25NPE405L-3DA200CZ |
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Advance Information
PowerNPTM NPe405L Embedded Processor Data Sheet
42
[UART0_DSR]
async
n/a
[UART0_DTR]
n/a
async
12
8
[UART0_RI]
async
n/a
[UART0_RTS]
n/a
async
12
8
UART0_Rx
async
n/a
UART0_Tx
n/a
async
12
8
[UART1_CTS]
async
n/a
[UART1_DCD]GPIO28
[HDLCEXTxEnA]
async
n/a
[UART1_DSR]
async
n/a
[UART1_DTR]
n/a
async
12
8
[UART1_RI]GPIO29
[HDLCEXTxEnB]
async
n/a
[UART1_RTS]
n/a
async
12
8
UART1_Rx
async
n/a
UART1_Tx
n/a
async
12
8
UARTSerClk
async
n/a
Interrupts Interface
[IRQ0:6]GPIO17:23
async
n/a
JTAG Interface
TCK
async
n/a
TDI
async
n/a
TDO
n/a
async
12
8
TMS
async
n/a
TRST
async
n/a
System Interface
[TrcClk]GPIO0
n/a
11.2
1.2
12
8
[TS1E]GPIO1
n/a
7.0
1.2
12
8
[TS2E]GPIO2
n/a
7.0
1.2
12
8
[TS1O]GPIO3
n/a
6.5
1.0
12
8
[TS2O]GPIO4
n/a
6.4
1.0
12
8
[TS3]GPIO5
n/a
6.4
1.0
12
8
[TS4]GPIO6
n/a
6.4
1.0
12
8
[TS5]GPIO7
n/a
6.6
1.0
12
8
[TS6]GPIO8
n/a
6.4
1.0
12
8
GPIO30
async
12
8
Halt
async
n/a
I/O Specications—200MHz (Part 2 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. The two-cycle SDRAM command interface is driven in cycle 1 and used in cycle 2. Output times in table are in cycle 1.
3. SDRAM output timing is relative to the rising edge of the internal PLB clock, which is an integral multiple of and rising-
edge aligned with SysClk. Therefore, SDRAM output timings in the table are shown relative to SysClk. Timings shown
are for a lumped 50pF load, however the interface has been verified for PC100-compliant operation using transmission
line circuit analysis.
4. SDRAM MemClkOut0:1 rising edge at package pin precedes the internal PLB clock by approximately 0.5ns for a
typical clock network or a lumped 10pF load.
5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(minimum)
Hold Time
(minimum)
Valid Delay
(maximum)
50pF load
Hold Time
(minimum)
50pF load
I/O H
(maximum)
I/O L
(minimum)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM25NPE405L-3FA200CZ | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA324 |
| IBM25NPE405L-3FA266CZ | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA324 |
| IBM25PPC405EP-3GB133CZ | 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA385 |
| IBM25PPC405EP-3GB133C | 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA385 |
| IBM25PPC405GP-3DD200C | RISC PROCESSOR, PBGA456 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM25NPE405L-3FA133C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25NPE405L-3FA133CZ | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25NPE405L-3FA200C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25NPE405L-3FA200CZ | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25NPE405L-3FA266C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
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