- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67682 > IBM25NPE405H-3DA200CZ 32-BIT, 200 MHz, RISC PROCESSOR, PBGA580 PDF資料下載
參數(shù)資料
| 型號： | IBM25NPE405H-3DA200CZ |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA580 |
| 封裝： | 35 MM, PLASTIC, EBGA-580 |
| 文件頁數(shù)： | 55/64頁 |
| 文件大小： | 1050K |
| 代理商： | IBM25NPE405H-3DA200CZ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁當前第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
Advance Information
PowerNPTM NPe405H Embedded Processor Data Sheet
59
PHY0Col[PHY0Rx1Er]l
async[0.1]
async[1.4]
n/a
1
PHY0CrS[PHY0CrS0DV]
async[0.1]
async[1.5]
n/a
1
PHY0RxClk
n/a
1, async
PHY0RxD0:3
[PHY0Rx0:1D0:1]
[PHY0Rx0:3D]
1.5
[0.8]
1.4
[1.3]
[0.2]
n/a
PHYRX
1
PHY0RxDV
[PHY0CRS1DV]
1.3[0.7]
1.3[1.3]
n/a
PHYRX
1
PHY0RxErr[PHY0Rx0Er]
1.3[0.7]
1.4[1.5]
n/a
PHYRX
1
PHY0TxClk[PHY0RefClk]
n/a
1, async
[PHY1RxD0:3]
[PHY1Rx2:3D0:1]
n/a
[PHY1Col]
[PHY1Rx3Er]
n/a
[PHY1CrS]
[PHY1CrS2DV]
n/a
[PHY1RxClk]
n/a
[PHY1RxDV]
[PHY1CrS3DV]
n/a
[PHY1RxErr]
[PHY1Rx2Er]
n/a
[PHY1TxClk]
n/a
HDLCEX Interface
HDLCEXRxClk
n/a
HDLCEXRxDataA:B
23.8
1.5
n/a
HDLCEXRxFS
24.2
0.8
n/a
HDLCEXTxClk
n/a
HDLCEXTxDataA:B
n/a
7.6
3.3
12
8
HDLCEXTxFS
24.2
0.8
n/a
HDLCEXTxEnA
[CGPIO24][UART1_RTS]
n/a
8.5
3.5
12
8
HDLCEXTxEnB
[CGPIO25][UART1_DTR]
n/a
8.9/
3.8
12
8
HDLCMP Interface
HDLCMPTxClk0:3
n/a
[HDLCMPTxClk4:7]
n/a
HDLCMPTxData0:3
12
8
I/O Specications—266MHz (Part 2 of 5)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. The two-cycle SDRAM command interface is driven in cycle 1 and used in cycle 2. Output times in table are in cycle 1.
3. SDRAM output timing is relative to the rising edge of the internal PLB clock, which is an integral multiple of and rising-
edge aligned with SysClk. Therefore, SDRAM output timings in the table are shown relative to SysClk. Timings shown
are for a lumped 50pF load, however the interface has been verified for PC100-compliant operation using transmission
line circuit analysis.
4. SDRAM MemClkOut0:1 rising edge at package pin precedes the internal PLB clock by approximately 0.5ns for a
typical clock network or a lumped 10pF load.
5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
6. PCI timings are for asynchronous operation up to 66MHz. PCI output hold time requirement is 1ns for 66MHz and 2ns
for 33MHz.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(minimum)
Hold Time
(minimum)
Valid Delay
(maximum)
50pF load
Hold Time
(minimum)
50pF load
I/O H
(maximum)
I/O L
(minimum)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM25NPE405L-3DA200CZ | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA324 |
| IBM25NPE405L-3FA200CZ | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA324 |
| IBM25NPE405L-3FA266CZ | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA324 |
| IBM25PPC405EP-3GB133CZ | 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA385 |
| IBM25PPC405EP-3GB133C | 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA385 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM25NPE405L-3FA133C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25NPE405L-3FA133CZ | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25NPE405L-3FA200C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25NPE405L-3FA200CZ | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25NPE405L-3FA266C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。