參數(shù)資料
型號: IBM25NPE405H-3DA200CZ
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA580
封裝: 35 MM, PLASTIC, EBGA-580
文件頁數(shù): 45/64頁
文件大?。?/td> 1050K
代理商: IBM25NPE405H-3DA200CZ
Advance Information
PowerNPTM NPe405H Embedded Processor Data Sheet
5
NPe405H Embedded Controller Functional Block Diagram
The NPe405H is designed using the IBM Microelectronics Blue LogicTM methodology in which major
functional blocks are integrated to create an application-specic ASIC product. This approach provides a
consistent way to generate complex ASICs using IBM CoreConnectTM Bus Architecture.
Note: IBM CoreConnect busses provide:
64-bit PLB interfaces up to 133MHz
32-bit OPB interfaces up to 66MHz
Address Map Support
The NPe405H incorporates two simple and separate address maps. The first is a fixed processor address
map that serves the PowerPC family of processors. This address map defines the possible contents of
various address regions which the processor can access. The second address map is for Device
Configuration Registers (DCR). This address map is accessed by software running on the NPe405H
processor through the use of mtdcr and mfdcr commands.
PPC405
Processor Core
DCU
ICU
DCR Bus
16KB
On-chip Peripheral Bus (OPB)
GPIO
IIC
MAL8
DMA
Bridge
Processor Local Bus (PLB)
SDRAM
PCI Bridge
External
Bus
Controller
Clock
Control
Reset
Power
Mgmt
JTAG
Trace
Timers
MMU
ZMII
Controller
OPB
Arb
- 28-bit addr
- 13-bit addr
- 32-bit data
I-Cache
8KB
D-Cache
(4-Channel)
66 MHz max (async)
133 MHz max
66 MHz max
DCRs
HDLCEX
See
Peripheral
Interface
Clock Timing table
HDLCMP
8 ports
8 channels
32 channels
2 ports
-32-bit data
External
Bus Master
Controller
Interrupt
Controller
Universal
x2
UART
x2
Ethernet
x4
MII, RMII, SMII
MAL64
x2
IEC
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