參數(shù)資料
型號(hào)： IBM25EMPPC750EBUB2330
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 233 MHz, RISC PROCESSOR, CBGA360
封裝： 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁(yè)數(shù)： 9/43頁(yè)
文件大?。?/td> 431K
代理商： IBM25EMPPC750EBUB2330
Preliminary and subject to change without notice
PPC740 and PPC750 Hardware Specifications
17 of 43
3.1.2.6 L2 Bus Output AC Specications
Table 12 provides the L2 bus output interface AC timing specications for the PPC750
as dened in Figure 8 .
Notes:
1. All outputs are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint
voltage (1.4 V) of the signal in question. The output timings are measured at the pins.
2.The outputs are valid for both single-ended and differential L2CLK modes. For ow-thru and pipelined
reg-reg synchronous burst SRAMs, L2CR[14-15] = 00 is recommended. For pipelined late-write syn-
chronous burst SRAMs, L2CR[14-15] = 01 is recommended.
3. All maximum timing specications assume CL = 20 pF.
4. This measurement assumes CL= 5 pF.
5. Reserved for future use.
6. Guaranteed by design and characterization, and not tested.
Figure 8 shows the L2 bus output timing diagrams for the PPC750.
Figure 8. L2 Bus Output Timing Diagrams
Table 12. L2 Bus Output Interface AC Timing Specications1
Operating conditions are specied in Section Table 2., "Recommended Operating Conditions" CL = 20 pF
3
Num
Characteristic
L2CR[14-15] is equivalent to:
Unit
Notes
002
01
10
11
Min
Max
Min
Max
Min
Max
Min
Max
26
L2SYNC_IN to output
valid
—
5.0
—
5.5
—
Rsv5
—
Rsv5
ns
27
L2SYNC_IN to output
hold
0.5
—
1.0
—
Rsv5
—
Rsv5
—ns
4
28
L2SYNC_IN to high
impedance
—
4.0
—
4.5
—
Rsv5
—
Rsv5
ns
6
27
VM
VM = Midpoint Voltage (1.4V)
L2SYNC_IN
26
ALL OUTPUTS
VM
28
L2DATA BUS
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