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參數(shù)資料
| 型號(hào)： | IBM13V25649AN |
| 廠商： | IBM Microeletronics |
| 英文描述： | 256K x 64 SGRAM SO DIMM（Small Outline Dual In-line Memory Modules）(256K x 64 144腳小外形雙列直插同步圖形RAM模塊) |
| 中文描述： | 256K × 64 SGRAM蘇內(nèi)存（小外形雙列直插式內(nèi)存模塊）（256K × 64 144腳小外形雙列直插同步圖形內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 9/14頁(yè) |
| 文件大?。?/td> | 224K |
| 代理商： | IBM13V25649AN |
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IBM13V25649AN IBM13V51649AN
256K/512K x 64 SGRAM SO DIMM
88H4121.E24358
Revised 1/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 14
Timing Specifications and Conditions
(0
°
C
≤
t
A
≤
70
°
C; V
CC
/V
CCQ
= 3.3V
±
0.3V)
1. All voltages are referenced to VSS (GND).
2. Icc depends on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open.
3. Enables on-chip refresh and address counters.
4. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0
°
C
≤
TA
≤
70
°
C).
5. An initial pause of 100ms is required after power up, followed by two Auto Refresh commands to ensure proper device operation.
6. The timing specifications assume a transition time (tT = 1ns).
7. AC timing tests have VIL = 0.8V and VIH = 2.0V with timing reference to 1.4V crossover point.
I/O Timing Diagrams
50
V
T
=1.4V
30pF
Z
0
=50
Vout
LVTTL A.C. Test Load
tCH
tCK
tCL
tSetup
tHold
1.4V
1.4V
0.8V
2.0V
1.4V
0.8V
CLK
Input
Output
tAC
Undefined
Dout
tOH
2.0V
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