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參數(shù)資料
| 型號： | IBM13V25649AN |
| 廠商： | IBM Microeletronics |
| 英文描述： | 256K x 64 SGRAM SO DIMM（Small Outline Dual In-line Memory Modules）(256K x 64 144腳小外形雙列直插同步圖形RAM模塊) |
| 中文描述： | 256K × 64 SGRAM蘇內(nèi)存（小外形雙列直插式內(nèi)存模塊）（256K × 64 144腳小外形雙列直插同步圖形內(nèi)存模塊） |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 224K |
| 代理商： | IBM13V25649AN |
IBM13V25649AN IBM13V51649AN
256K/512K x 64 SGRAM SO DIMM
88H4121.E24358
Revised 1/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 14
Features
144 Pin Graphics JEDEC Standard, 8 Byte Syn-
chronous Small Outline Dual-In-line Memory
Module
Performance:
Speed Grade
Clock Frequency
Clock Cycle
Clock Access Time
Inputs and outputs are LVTTL (3.3V) compatible
Single 3.3V
±
0.3V Power Supply
SDRAMs have 2 internal banks; module has 2
banks
8 Column Block Write and Write-per-Bit mode
Independent byte operation via DQM0-7
Programmable Operation:
- CAS Latency: 1, 2, 3
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8, Full-Page (Full-
Page supports Sequential burst only)
- Operation: Burst Read and Write or Multiple
Burst Read with Single Write
Auto Refresh (CBR)
Automatic and controlled Precharge Commands
9/8/1 Addressing (Row/Column/Bank)
1K refresh cycles in 16ms
Parallel Presence Detects
Card size:
2.66" x 1.0" x 0.111"; gold contacts (256K x 64)
2.66" x 1.15" x 0.179"; gold contacts (512K x 64)
SGRAMS in 100-pin LQFP Package
Description
IBM13V25649AN and IBM13V51649AN are 144-pin
Synchronous GRAM Small Outline Dual In-line
Memory Modules (SO DIMMs) organized as
256Kx64 and 512Kx64 high-speed memory arrays.
The SO DIMMs use two and four 256Kx32 SGRAMs
respectively in 20x14mil LQFP packages. The SO
DIMMs achieve high speed data transfer rates of up
to 133MHz by employing a prefetch/pipeline hybrid
architecture that supports the JEDEC 1N rule while
allowing very low burst power.
All control, address, and data input/output circuits
are synchronized with the positive edge of the exter-
nally supplied clock inputs.
All inputs are sampled at the positive edge of each
externally supplied clock (CK0, CK1). Internal oper-
ating modes are defined by combinations of the
RAS, CAS, WE, CS, DQMB, and CKE signals. A
command decoder initiates the necessary timings
for each operation. A 10-bit address bus accepts
address information in a row/column multiplexing
arrangement.
Prior to any access operation, the CAS latency,
burst type, burst length, and burst operation type
must be programmed into the SO DIMM by address
inputs A0-A9 during the mode register set cycle.
SGRAMs differ from Synchronous DRAMs
(SDRAMs) by providing 8 Column Block Write and
Write-per-Bit (WPB) functions. The Block Write and
WPB functions may be combined with individual
byte enables (DQM0 - DQM7).
The SO DIMMs include three Parallel Presence
Detect pins, which are dotted onto data pins DQ29 -
DQ31. These pins can be sensed when the SGRAM
outputs are inactive (the 3 pins are either ‘NC’ or tie
to V
CC
via a 4.7K ohm resistor). The Parallel PDs
identify the minimum cycle time supported by the
SO DIMMs.
All IBM 144-pin SO DIMMs provide a high perfor-
mance, flexible 8-byte interface in a 2.65" long
space-saving footprint.
7R5
133
7.5
7
10
100
10
9
Units
MHz
ns
ns
Card Outlines
1
143
144
(Front)
(Back) 2
49
50
51
52
1
143
144
(Front)
(Back) 2
49
50
51
52
256K x 64
512K x 64
IBM11M4730C4M x 72 E12/10, 5.0V, Au.
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