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參數(shù)資料
| 型號： | IBM13T4644MPE |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 64 PC100 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(4M x 64 PC100小外形雙列直插式同步動態(tài)RAM模塊) |
| 中文描述： | 4米× 64蘇PC100的SDRAM的內(nèi)存（小外型雙線內(nèi)存模組）（4米× 64 PC100的小外形雙列直插式同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 269K |
| 代理商： | IBM13T4644MPE |
IBM13T4644MPE
4M x 64 PC100 SDRAM SO DIMM
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 17
45L7084.E93888B
10/99
AC Characteristics
(T
A
= 0 to +70
°
C, V
DD
= 3.3V
±
0.3V)
An initial pause of 200
μ
s, with DQMB0-7 and CKE0-CKE1 held high, is required after power-up. A Precharge All Banks command must
be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation.
1. The Transition time is measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
2. In addition to meeting the transition rate specification, the clock and CKE must transit between V
IH
and V
IL
(or between V
IL
and V
IH
)
in a monotonic manner.
3. Load Circuit: AC timing tests have V
IL
= 0.8 V and V
IH
= 2.0 V with the timing referenced to the 1.40V crossover point
4. Load Circuit: AC measurements assume t
T
=1.2 ns.
AC Characteristics Diagram
Clock and Clock Enable Parameters
Symbol
Parameter
-360
(CL, t
RCD
, t
RP
= 3 / 2 / 2)
Units
Notes
Min.
Max.
t
CK3
Clock Cycle Time, CAS Latency = 3
10
1000
ns
t
CK2
Clock Cycle Time, CAS Latency = 2
15
1000
ns
1
t
AC3
Clock Access Time, CAS Latency = 3
—
6
ns
2
t
AC2
Clock Access Time, CAS Latency = 2
—
9
ns
2
t
CKH
Clock High Pulse Width
3
—
ns
3
t
CKL
Clock Low Pulse Width
3
—
ns
3
t
CES
Clock Enable Set-up Time
2
—
ns
t
CEH
Clock Enable Hold Time
1
—
ns
t
SB
Power down mode Entry Time
0
10
ns
t
T
Transition Time (Rise and Fall)
0.5
10
ns
1. For -360 sort, 66Mhz clock: CAS Latency = 2.
2. Access time is measured at 1.4V. See AC Characteristics: notes: 1, 2, 3, 6, 7 and load circuit B.
3. t
CKH
is the pulse width of CLK measured from the positive edge to the negative edge referenced to V
IH
(min). t
CKL
is the pulse
width of CLK measured from the negative edge to the positive edge referenced to V
IL
(max).
Output
Input
Clock
t
OH
t
SETUP
t
HOLD
t
AC
t
LZ
1.4V
1.4V
V
IL
1.4V
t
T
t
CKH
t
CKL
Output
50pF
Z
o
= 50
AC Output Load Circuit
V
IH
Discontinued (4/1/00 last order; 7/31/00 - last ship)
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