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參數(shù)資料
| 型號： | IBM13T4644MPE |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 64 PC100 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(4M x 64 PC100小外形雙列直插式同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 4米× 64蘇PC100的SDRAM的內(nèi)存（小外型雙線內(nèi)存模組）（4米× 64 PC100的小外形雙列直插式同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 6/17頁 |
| 文件大小： | 269K |
| 代理商： | IBM13T4644MPE |
IBM13T4644MPE
4M x 64 PC100 SDRAM SO DIMM
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 6 of 17
45L7084.E93888B
10/99
Serial Presence Detect
Byte #
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
80
08
04
0C
08
01
4000
01
A0
60
00
80
10
00
01
8F
04
06
01
01
00
Notes
0
1
2
3
4
5
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Banks
Data Width of Assembly
Voltage Interface Level of this Assembly
SDRAM Device Cycle Time at CL=3
SDRAM Device Access Time from Clock at CL=3
DIMM Configuration Type
Refresh Rate/Type
Primary SDRAM Device Width
Error Checking SDRAM Device Width
SDRAM Device Attr: Min Clk Delay, Random Col Access
SDRAM Device Attributes: Burst Lengths Supported
SDRAM Device Attributes: Number of Device Banks
SDRAM Device Attributes: CAS Latencies Supported
SDRAM Device Attributes: CS Latency
SDRAM Device Attributes: WE Latency
SDRAM Module Attributes
128
256
SDRAM
12
8
1
x64
LVTTL
10.0ns
6.0ns
Non-Parity
SR/1x(15.625
μ
s)
x16
N/A
1 Clock
1,2,4,8, Full Page
4
2, 3
0
0
Unbuffered
Wr-1/Rd Burst, Precharge All,
Auto-Precharge,
V
DD
±
10%
15.0ns
9.0ns
N/A
N/A
20ns
20ns
20ns
50ns
32MB
2.0
1.0
2.0
1.0
Undefined
1.2
Checksum Data
IBM
Toronto, Canada
Vimercate, Italy
6 - 7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SDRAM Device Attributes: General
0E
23
24
25
26
27
28
29
30
31
32
33
34
35
Minimum Clock Cycle at CL=2
Maximum Data Access Time (t
AC
) from Clock at CL=2
Minimum Clock Cycle Time at CL=1
Maximum Data Access Time (t
AC
) from Clock at CL=1
Minimum Row Precharge Time (t
RP
)
Minimum Row Active to Row Active delay (t
RRD
)
Minimum RAS to CAS delay (t
RCD
)
Minimum RAS Pulse width (t
RAS
)
Module Bank Density
Address and Command Setup Time Before Clock
Address and Command Hold Time After Clock
Data Input Setup Time Before Clock
Data Input Hold Time After Clock
Reserved
SPD Revision
Checksum for bytes 0 - 62
Manufacturers’ JEDEC ID Code
F0
90
00
00
14
14
14
32
08
20
10
20
10
00
12
cc
36 - 61
62
63
64 - 71
1
A400000000000000
91
53
313354343634344D50
rr2D33363054202020
rr20
yyww
ssssssss
00
64
72
Module Manufacturing Location
73 - 90
Module Part Number
ASCII ‘13T4644MP”R”-360’
2, 3
91 - 92
93 - 94
95 - 98
99 - 125
126
Module Revision Code
Module Manufacturing Date
Module Serial Number
Reserved
Module Supports this Clock Frequency
“R” plus ASCII blank
Year/Week Code
Serial Number
Undefined
100 MHz
CK0,CL3, concurrent
AP
Undefined
2, 3
4, 5
6
127
Attributes for Clock Frequency defined in byte 126
85
128 - 255 Open for Customer Use
00
1. cc = Checksum Data byte, 00-FF (Hex)
2. “R” = Alphanumeric revision code, A-Z, 0-9
3. rr = ASCII coded revision code byte “R”
4. yy = Binary coded decimal year code, 00-99 (Decimal)
‘
00-63 (Hex)
5. ww = Binary coded decimal week code, 01-52 (Decimal)
‘
01-34 (Hex)
6. ss = Serial number data byte, 00-FF (Hex)
Discontinued (4/1/00 last order; 7/31/00 - last ship)
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