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參數(shù)資料
| 型號(hào)： | IBM13T2649JC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 2M x 64 SDRAM SO DIMM(Small Outline Dual In-Line Memory Module)(2M x 64 小外形雙列直插同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 200萬(wàn)蘇× 64 SDRAM的內(nèi)存（小外形雙列內(nèi)存模組）（2米× 64小外形雙列直插同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 9/15頁(yè) |
| 文件大?。?/td> | 299K |
| 代理商： | IBM13T2649JC |
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IBM13T2649JC
2M x 64 SDRAM SO DIMM
75H5376
GA14-4476-02
Rev 3/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 15
Operating Currents
(T
A
= 0 to +70C, V
DD
= 3.3V
±
0.3V)
Symbol
Parameter
Test Condition
CAS
Latency
CL=1
CL=2
CL=3
CL=1
CL=2
CL=3
CL=1
CL=2
CL=3
CL=1
CL=2
CL=3
t
RC
(min)
Speed
Sort
-10
-10
-10
-10
-10
-10
-10
-10
-10
-10
-10
-10
Organization
X64
760
840
1000
600
800
1000
520
760
1000
480
720
1000
Units
Notes
I
DD5
Operating Current
Burst Length = 1
t
RC
=
t
RC
(min)
t
CK
≥
t
CK
(min)
I
O
= 0mA
t
RC
=
t
RC
(min)
t
CK
≥
t
(min)
I
O
= 0mA
t
RC
=
t
RC
(min)
t
CK
≥
t
CK
(min)
I
O
= 0mA
t
RC
=
t
RC
(min)
t
CK
≥
t
(min)
I
O
= 0mA
90 ns
90 ns
90 ns
120 ns
105 ns
125 ns
180 ns
135 ns
120 ns
300 ns
195 ns
160 ns
t
RC
=
∞
t
CK
=30 ns
t
RC
=
∞
t
CK
=15 ns
t
RC
=
∞
t
CK
=10 ns
t
RC
=
∞
t
CK
=30 ns
t
RC
=
∞
t
CK
=15 ns
t
RC
=
∞
t
CK
=10 ns
mA
1, 2
I
DD6
Operating Current
Burst Length = 2
mA
1, 2, 3
I
DD7
Operating Current
Burst Length = 4
mA
1, 2, 3
I
DD8
Operating Current
Burst Length = 8
mA
1, 2, 3
I
DD9
Operating Current
Burst Length = Full Page
t
RC
=
Infinity
t
CK
≥
t
CK
(min)
I
O
= 0mA
CL=1
-10
360
mA
1, 2, 3
CL=2
-10
600
CL=3
-10
840
I
DD10
Operating Current
1N Rule
(Continuous Read/Write cycles
with new column address regis-
tered each clock cycle)
t
RC
=
Infinity
t
CK
≥
t
CK
(min)
I
O
= 0mA
CL=1
-10
680
mA
1, 2
CL=2
-10
1040
CL=3
-10
1400
I
DDA
Serial PD Device Active Power
Supply
Current
SCL Clock Frequency = 100kHz
1.0
mA
4
1. The specified values are obtained with the output open.
2. The specified values are valid when addresses and DQ’s are changed no more than once during t
CK
(min).
3. The specified values are obtained when the programmed burst length is executed to completion without interruption by a subse-
quent burst Read or Write cycle.
4. Input pulse levels V
DD
x 0.1 to V
DD
x 0.9, input rise and fall times 10ns, input and output timing levels V
DD
x 0.5, output load 1 TTL
gate and CL = 100pf.
Discontinued (12/98 - last order; 9/99 last ship)
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